261 lines
5.7 KiB
ArmAsm
261 lines
5.7 KiB
ArmAsm
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <mach/imx35-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <asm/cache-l2x0.h>
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#include <asm-generic/memory_layout.h>
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#include <asm/barebox-arm-head.h>
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#include "board-mx35_3stack.h"
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#define CSD0_BASE_ADDR 0x80000000
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#define CSD1_BASE_ADDR 0x90000000
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#define ESDCTL_BASE_ADDR 0xB8001000
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define writeb(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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strb r1, [r0];
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/* Assuming 24MHz input clock */
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#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
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#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
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#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
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.section ".text_bare_init","ax"
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ARM_PPMRR: .word 0x40000015
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L2CACHE_PARAM: .word 0x00030024
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CCM_CCMR_W: .word 0x003F4208
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CCM_PDR0_W: .word 0x00001000
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MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
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MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
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PPCTL_PARAM_W: .word PPCTL_PARAM_300
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CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR
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.globl reset
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reset:
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common_reset r0
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mrc 15, 0, r1, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1 << 11) /* Flow prediction (Z) */
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orr r1, r1, #(1 << 22) /* unaligned accesses */
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orr r1, r1, #(1 << 21) /* Low Int Latency */
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mcr 15, 0, r1, c1, c0, 0
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mov r0, #0
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mcr 15, 0, r0, c15, c2, 4
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/*
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* Branch predicition is now enabled. Flush the BTAC to ensure a valid
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* starting point. Don't flush BTAC while it is disabled to avoid
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* ARM1136 erratum 408023.
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 6 /* flush entire BTAC */
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mov r0, #0
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/* Also setup the Peripheral Port Remap register inside the core */
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ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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/*
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* End of ARM1136 init
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*/
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ldr r0, CCM_BASE_ADDR_W
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ldr r2, CCM_CCMR_W
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str r2, [r0, #MX35_CCM_CCMR]
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ldr r3, MPCTL_PARAM_532_W /* consumer path*/
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/* Set MPLL, arm clock and ahb clock */
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str r3, [r0, #MX35_CCM_MPCTL]
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ldr r1, PPCTL_PARAM_W
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str r1, [r0, #MX35_CCM_PPCTL]
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ldr r1, CCM_PDR0_W
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str r1, [r0, #MX35_CCM_PDR0]
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ldr r1, [r0, #MX35_CCM_CGR0]
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orr r1, r1, #0x00300000
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str r1, [r0, #MX35_CCM_CGR0]
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ldr r1, [r0, #MX35_CCM_CGR1]
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orr r1, r1, #0x00000C00
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orr r1, r1, #0x00000003
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str r1, [r0, #MX35_CCM_CGR1]
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/* Skip SDRAM initialization if we run from RAM */
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cmp pc, #CSD0_BASE_ADDR
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bls 1f
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cmp pc, #CSD1_BASE_ADDR
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bhi 1f
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b board_init_lowlevel_return
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1:
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ldr r0, =ESDCTL_BASE_ADDR
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mov r3, #0x2000
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str r3, [r0, #0x0]
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str r3, [r0, #0x8]
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/* ip(r12) has used to save lr register in upper calling */
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mov fp, lr
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/* setup bank 0 */
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #MX35_CSD0_BASE_ADDR
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bl setup_sdram_bank
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/* setup bank 1 */
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #MX35_CSD1_BASE_ADDR
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bl setup_sdram_bank
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mov lr, fp
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ldr r3, =ESDCTL_DELAY_LINE5
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str r3, [r0, #0x30]
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
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b imx35_barebox_boot_nand_external
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#endif /* CONFIG_NAND_IMX_BOOT */
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b board_init_lowlevel_return
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/*
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* r0: ESDCTL control base, r1: sdram slot base
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* r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base
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*/
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setup_sdram_bank:
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mov r3, #0xE /* 0xA + 0x4 */
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tst r2, #0x1
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orreq r3, r3, #0x300 /* DDR2 */
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str r3, [r0, #0x10]
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bic r3, r3, #0x00A
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str r3, [r0, #0x10]
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beq 2f
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mov r3, #0x20000
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1: subs r3, r3, #1
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bne 1b
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2: tst r2, #0x1
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ldreq r3, =ESDCTL_DDR2_CONFIG
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ldrne r3, =ESDCTL_MDDR_CONFIG
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cmp r1, #CSD1_BASE_ADDR
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strlo r3, [r0, #0x4]
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strhs r3, [r0, #0xC]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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tst r2, #0x1
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bne skip_set_mode
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_DDR2_EMR2
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EMR3
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EN_DLL
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_RESET_DLL
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strb r3, [r1, r4]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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skip_set_mode:
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xA2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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strb r3, [r1]
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strb r3, [r1]
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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ldreq r4, =ESDCTL_DDR2_MR
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ldrne r4, =ESDCTL_MDDR_MR
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mov r3, #0xDA
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strb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
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streqb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_EN_DLL
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ldrne r4, =ESDCTL_MDDR_EMR
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strb r3, [r1, r4]
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0x82228080
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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moveq r4, #0x20000
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movne r4, #0x200
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1: subs r4, r4, #1
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bne 1b
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str r3, [r1, #0x100]
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ldr r4, [r1, #0x100]
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cmp r3, r4
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movne r3, #1
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moveq r3, #0
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mov pc, lr
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