74 lines
1.5 KiB
C
74 lines
1.5 KiB
C
#define BCM2835_MCI_SLOTISR_VER 0xfc
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#define MIN_FREQ 400000
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#define BLOCK_SHIFT 16
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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#define CONTROL0_HISPEED (1 << 2)
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#define CONTROL0_4DATA (1 << 1)
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#define CONTROL1_DATARST (1 << 26)
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#define CONTROL1_CMDRST (1 << 25)
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#define CONTROL1_HOSTRST (1 << 24)
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#define CONTROL1_CLKSELPROG (1 << 5)
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#define CONTROL1_CLKENA (1 << 2)
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#define CONTROL1_CLK_STABLE (1 << 1)
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#define CONTROL1_INTCLKENA (1 << 0)
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#define CONTROL1_CLKMSB 6
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#define CONTROL1_CLKLSB 8
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#define CONTROL1_TIMEOUT (0x0E << 16)
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#define MAX_CLK_DIVIDER_V3 2046
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#define MAX_CLK_DIVIDER_V2 256
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/*this is only for mbox comms*/
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#define BCM2835_MBOX_PHYSADDR 0x2000b880
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#define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
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#define BCM2835_MBOX_CLOCK_ID_EMMC 1
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#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
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#define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
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#define BCM2835_MBOX_PROP_CHAN 8
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#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000
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struct bcm2835_mbox_regs {
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u32 read;
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u32 rsvd0[5];
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u32 status;
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u32 config;
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u32 write;
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};
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struct bcm2835_mbox_hdr {
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u32 buf_size;
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u32 code;
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};
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struct bcm2835_mbox_tag_hdr {
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u32 tag;
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u32 val_buf_size;
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u32 val_len;
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};
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struct bcm2835_mbox_tag_get_clock_rate {
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struct bcm2835_mbox_tag_hdr tag_hdr;
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union {
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struct {
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u32 clock_id;
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} req;
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struct {
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u32 clock_id;
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u32 rate_hz;
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} resp;
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} body;
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};
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struct msg_get_clock_rate {
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struct bcm2835_mbox_hdr hdr;
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struct bcm2835_mbox_tag_get_clock_rate get_clock_rate;
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u32 end_tag;
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};
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