239 lines
6.8 KiB
C
239 lines
6.8 KiB
C
/*
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* Copyright (C) 2013 Sascha Hauer, Pengutronix
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* Copyright (C) 2015 PHYTEC Messtechnik GmbH,
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* Author: Stefan Christ <s.christ@phytec.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*
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*/
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#define pr_fmt(fmt) "phySOM-i.MX6: " fmt
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#include <malloc.h>
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#include <envfs.h>
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#include <environment.h>
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#include <bootsource.h>
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#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <of.h>
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#include <mach/bbu.h>
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#include <platform_data/eth-fec.h>
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#include <mfd/imx6q-iomuxc-gpr.h>
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#include <linux/clk.h>
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#include <linux/micrel_phy.h>
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#include <globalvar.h>
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#include <linux/micrel_phy.h>
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#include <mach/iomux-mx6.h>
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#include <mach/imx6.h>
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#define PHYFLEX_MODULE_REV_1 0x1
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#define PHYFLEX_MODULE_REV_2 0x2
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#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
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MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS
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#define MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(GPIO_2_11_PD_CTL))
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#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, GPIO_2_11_PD_CTL)
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#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11)
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static void phyflex_err006282_workaround(void)
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{
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/*
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* Boards beginning with 1362.2 have the SD4_DAT3 pin connected
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* to the CMIC. If this pin isn't toggled within 10s the boards
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* reset. The pin is unconnected on older boards, so we do not
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* need a check for older boards before applying this fixup.
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*/
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);
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mdelay(2);
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gpio_direction_output(MX6_PHYFLEX_ERR006282, 1);
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mdelay(2);
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gpio_set_value(MX6_PHYFLEX_ERR006282, 0);
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if (cpu_is_mx6q() || cpu_is_mx6d())
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mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD);
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else if (cpu_is_mx6dl() || cpu_is_mx6s())
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mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11);
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gpio_direction_input(MX6_PHYFLEX_ERR006282);
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}
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static unsigned int pfla02_module_revision;
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static unsigned int get_module_rev(void)
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{
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unsigned int val = 0;
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val = gpio_get_value(IMX_GPIO_NR(2, 12));
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val |= (gpio_get_value(IMX_GPIO_NR(2, 13)) << 1);
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val |= (gpio_get_value(IMX_GPIO_NR(2, 14)) << 2);
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val |= (gpio_get_value(IMX_GPIO_NR(2, 15)) << 3);
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return 16 - val;
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}
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int ksz8081_phy_fixup(struct phy_device *phydev)
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{
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phy_write(phydev, 0x1f, 0x8190);
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phy_write(phydev, 0x16, 0x202);
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return 0;
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}
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static int imx6ul_setup_fec(void)
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{
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void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
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uint32_t val;
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struct clk *clk;
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phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
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ksz8081_phy_fixup);
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clk = clk_lookup("enet_ptp");
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if (IS_ERR(clk))
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goto err;
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clk_enable(clk);
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clk = clk_lookup("enet_ref");
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if (IS_ERR(clk))
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goto err;
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clk_enable(clk);
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clk = clk_lookup("enet_ref_125m");
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if (IS_ERR(clk))
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goto err;
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clk_enable(clk);
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val = readl(gprbase + IOMUXC_GPR1);
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/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
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val &= ~(1 << 13);
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val |= (1 << 17);
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/* Use 50M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], set gpr1[18]*/
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val &= ~(1 << 14);
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val |= (1 << 18);
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writel(val, gprbase + IOMUXC_GPR1);
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return 0;
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err:
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pr_err("Setting up DFEC\n");
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return -EIO;
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}
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static int physom_imx6_devices_init(void)
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{
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int ret;
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char *environment_path, *default_environment_path;
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char *envdev, *default_envdev;
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if (of_machine_is_compatible("phytec,imx6q-pfla02")
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|| of_machine_is_compatible("phytec,imx6dl-pfla02")
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|| of_machine_is_compatible("phytec,imx6s-pfla02")) {
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phyflex_err006282_workaround();
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pfla02_module_revision = get_module_rev();
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globalvar_add_simple_int("board.revision", &pfla02_module_revision, "%u");
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pr_info("Module Revision: %u\n", pfla02_module_revision);
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barebox_set_hostname("phyFLEX-i.MX6");
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default_environment_path = "/chosen/environment-spinor";
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default_envdev = "SPI NOR flash";
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} else if (of_machine_is_compatible("phytec,imx6q-pcaaxl3")) {
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barebox_set_hostname("phyCARD-i.MX6");
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default_environment_path = "/chosen/environment-nand";
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default_envdev = "NAND flash";
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} else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
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|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
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barebox_set_hostname("phyCORE-i.MX6");
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default_environment_path = "/chosen/environment-spinor";
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default_envdev = "SPI NOR flash";
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} else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
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barebox_set_hostname("phyCORE-i.MX6UL");
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default_environment_path = "/chosen/environment-nand";
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default_envdev = "NAND flash";
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imx6ul_setup_fec();
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} else
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return 0;
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switch (bootsource_get()) {
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case BOOTSOURCE_MMC:
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environment_path = basprintf("/chosen/environment-sd%d",
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bootsource_get_instance() + 1);
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envdev = "MMC";
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break;
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case BOOTSOURCE_NAND:
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environment_path = basprintf("/chosen/environment-nand");
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envdev = "NAND flash";
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break;
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case BOOTSOURCE_SPI:
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environment_path = basprintf("/chosen/environment-spinor");
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envdev = "SPI NOR flash";
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break;
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default:
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environment_path = basprintf(default_environment_path);
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envdev = default_envdev;
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break;
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}
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if (environment_path) {
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ret = of_device_enable_path(environment_path);
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if (ret < 0)
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pr_warn("Failed to enable environment partition '%s' (%d)\n",
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environment_path, ret);
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free(environment_path);
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}
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pr_notice("Using environment in %s\n", envdev);
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if (of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
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imx6_bbu_internal_mmc_register_handler("mmc3",
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"/dev/mmc3",
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BBU_HANDLER_FLAG_DEFAULT);
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} else {
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imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
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}
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defaultenv_append_directory(defaultenv_physom_imx6);
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/* Overwrite file /env/init/automount */
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if (of_machine_is_compatible("phytec,imx6q-pcm058-nand")
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|| of_machine_is_compatible("phytec,imx6q-pcm058-emmc")
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
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|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
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defaultenv_append_directory(defaultenv_physom_imx6_phycore);
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} else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
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defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
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}
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return 0;
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}
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device_initcall(physom_imx6_devices_init);
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