114 lines
4.6 KiB
C
114 lines
4.6 KiB
C
/*
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* Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>
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* Copyright (C) 2015 PHYTEC Messtechnik GmbH,
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* Author: Stefan Christ <s.christ@phytec.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <debug_ll.h>
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#include <common.h>
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#include <linux/sizes.h>
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#include <io.h>
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#include <image-metadata.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <asm/sections.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mach/imx6.h>
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static inline void setup_uart(void)
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{
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void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
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writel(0x4, iomuxbase + 0x01f8);
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imx6_ungate_all_peripherals();
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imx6_uart_setup_ll();
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putc_ll('>');
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}
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#define SZ_4G 0xEFFFFFF8
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BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_128M, IMD_TYPE_PARAMETER, "memsize=128", 0);
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BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_256M, IMD_TYPE_PARAMETER, "memsize=256", 0);
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BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_512M, IMD_TYPE_PARAMETER, "memsize=512", 0);
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BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0);
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BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_2G, IMD_TYPE_PARAMETER, "memsize=2048", 0);
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BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_4G, IMD_TYPE_PARAMETER, "memsize=4096", 0);
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static void __noreturn start_imx6_phytec_common(uint32_t size,
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bool do_early_uart_config,
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void *fdt_blob_fixed_offset)
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{
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int cpu_type = __imx6_cpu_type();
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void *fdt;
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if (cpu_type == IMX6_CPUTYPE_IMX6UL) {
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arm_cpu_lowlevel_init();
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/* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */
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arm_setup_stack(0x00910000 - 8);
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} else {
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imx6_cpu_lowlevel_init();
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/* OCRAM Free Area is 0x00907000 to 0x00938000 (196KB) */
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arm_setup_stack(0x00920000 - 8);
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}
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if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL))
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setup_uart();
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fdt = fdt_blob_fixed_offset - get_runtime_offset();
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if (cpu_type == IMX6_CPUTYPE_IMX6UL)
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barebox_arm_entry(0x80000000, size, fdt);
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else
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barebox_arm_entry(0x10000000, size, fdt);
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}
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#define PHYTEC_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \
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ENTRY_FUNCTION(name, r0, r1, r2) \
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{ \
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extern char __dtb_##fdt_name##_start[]; \
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\
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IMD_USED(physom_mx6_memsize_##memory_size); \
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\
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start_imx6_phytec_common(memory_size, do_early_uart_config, \
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__dtb_##fdt_name##_start); \
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}
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PHYTEC_ENTRY(start_phytec_pbaa03_1gib, imx6q_phytec_pbaa03, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_pbaa03_1gib_1bank, imx6q_phytec_pbaa03, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_pbaa03_2gib, imx6q_phytec_pbaa03, SZ_2G, true);
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PHYTEC_ENTRY(start_phytec_pbab01_512mb_1bank, imx6q_phytec_pbab01, SZ_512M, true);
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PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_pbab01_1gib_1bank, imx6q_phytec_pbab01, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_pbab01_2gib, imx6q_phytec_pbab01, SZ_2G, true);
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PHYTEC_ENTRY(start_phytec_pbab01_4gib, imx6q_phytec_pbab01, SZ_4G, true);
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PHYTEC_ENTRY(start_phytec_pbab01dl_1gib, imx6dl_phytec_pbab01, SZ_1G, false);
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PHYTEC_ENTRY(start_phytec_pbab01dl_1gib_1bank, imx6dl_phytec_pbab01, SZ_1G, false);
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PHYTEC_ENTRY(start_phytec_pbab01s_128mb_1bank, imx6s_phytec_pbab01, SZ_128M, false);
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PHYTEC_ENTRY(start_phytec_pbab01s_256mb_1bank, imx6s_phytec_pbab01, SZ_256M, false);
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PHYTEC_ENTRY(start_phytec_pbab01s_512mb_1bank, imx6s_phytec_pbab01, SZ_512M, false);
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PHYTEC_ENTRY(start_phytec_phyboard_alcor_1gib, imx6q_phytec_phyboard_alcor, SZ_1G, false);
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PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_subra, SZ_512M, false);
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PHYTEC_ENTRY(start_phytec_phyboard_subra_1gib_1bank, imx6q_phytec_phyboard_subra, SZ_1G, false);
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PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_som_emmc, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
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PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);
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