95 lines
2.7 KiB
C
95 lines
2.7 KiB
C
/*
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* (C) Copyright 2004-2009
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/omap4-mux.h>
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#include <mach/omap4-silicon.h>
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#include <mach/omap4-clock.h>
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#include <mach/syslib.h>
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#include <asm/barebox-arm.h>
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void set_muxconf_regs(void);
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static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = {
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.tim1 = 0x0EEB0662,
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.tim2 = 0x20370DD2,
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.tim3 = 0x00BFC33F,
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.phy_ctrl_1 = 0x849FF408,
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.ref_ctrl = 0x00000618,
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.config_init = 0x80001AB1,
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.config_final = 0x80001AB1,
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.zq_config = 0xd0093215,
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.mr1 = 0x83,
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.mr2 = 0x4
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};
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static noinline void pcaaxl2_init_lowlevel(void)
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{
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struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
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struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
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struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2;
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struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2;
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struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2;
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struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2;
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set_muxconf_regs();
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omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
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/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
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omap4_scale_vcores();
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writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL);
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/* Configure all DPLL's at 100% OPP */
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omap4_configure_mpu_dpll(&mpu);
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omap4_configure_iva_dpll(&iva);
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omap4_configure_per_dpll(&per);
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omap4_configure_abe_dpll(&abe);
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omap4_configure_usb_dpll(&usb);
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/* Enable all clocks */
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omap4_enable_all_clocks();
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sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */
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sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */
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sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */
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sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
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sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
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board_init_lowlevel_return();
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}
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void board_init_lowlevel(void)
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{
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u32 r;
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if (get_pc() > 0x80000000)
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return;
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r = 0x4030d000;
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__asm__ __volatile__("mov sp, %0" : : "r"(r));
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pcaaxl2_init_lowlevel();
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}
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