232 lines
7.1 KiB
C
232 lines
7.1 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <init.h>
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#include <common.h>
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#include <sizes.h>
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#include <environment.h>
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#include <io.h>
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#include <mach/imx5.h>
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#include <mach/imx51-regs.h>
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#include <mach/revision.h>
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#include <mach/clock-imx51_53.h>
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#include <mach/generic.h>
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#define IIM_SREV 0x24
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static int imx51_silicon_revision(void)
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{
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void __iomem *iim_base = IOMEM(MX51_IIM_BASE_ADDR);
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u32 rev = readl(iim_base + IIM_SREV) & 0xff;
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switch (rev) {
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case 0x0:
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return IMX_CHIP_REV_2_0;
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case 0x10:
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return IMX_CHIP_REV_3_0;
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default:
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return IMX_CHIP_REV_UNKNOWN;
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}
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return 0;
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}
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int imx51_init(void)
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{
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imx_set_silicon_revision("i.MX51", imx51_silicon_revision());
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imx51_boot_save_loc((void *)MX51_SRC_BASE_ADDR);
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add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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return 0;
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}
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int imx51_devices_init(void)
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{
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add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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add_generic_device("imx-iomuxv3", 0, NULL, MX51_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx51-ccm", 0, NULL, MX51_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 1, NULL, MX51_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 2, NULL, MX51_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx21-wdt", 0, NULL, MX51_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx51-usb-misc", 0, NULL, MX51_OTG_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL);
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return 0;
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}
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/*
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* Saves the boot source media into the $bootsource environment variable
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*
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* This information is useful for barebox init scripts as we can then easily
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* use a kernel image stored on the same media that we launch barebox with
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* (for example).
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*
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* imx25 and imx35 can boot into barebox from several media such as
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* nand, nor, mmc/sd cards, serial roms. "mmc" is used to represent several
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* sources as its impossible to distinguish between them.
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*
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* Some sources such as serial roms can themselves have 3 different boot
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* possibilities (i2c1, i2c2 etc). It is assumed that any board will
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* only be using one of these at any one time.
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*
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* Note also that I suspect that the boot source pins are only sampled at
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* power up.
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*/
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#define DP_MFN_800_DIT 60 /* PL Dither mode */
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/*
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* Workaround for i.MX51 PLL errata. This is needed by all boards using the
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* i.MX51 silicon version up until (including) 3.0 running at 800MHz.
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* The PLL's in the i.MX51 processor can go out of lock due to a metastable
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* condition in an analog flip-flop when used at high frequencies.
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* This workaround implements an undocumented feature in the PLL (dither
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* mode), which causes the effect of this failure to be much lower (in terms
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* of frequency deviation), avoiding system failure, or at least decreasing
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* the likelihood of system failure.
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*/
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static void imx51_setup_pll800_bug(void)
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{
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void __iomem *base = (void *)MX51_PLL1_BASE_ADDR;
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u32 dp_config;
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volatile int i;
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imx5_setup_pll_864(base);
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dp_config = readl(base + MX5_PLL_DP_CONFIG);
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dp_config &= ~MX5_PLL_DP_CONFIG_AREN;
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writel(dp_config, base + MX5_PLL_DP_CONFIG);
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/* Restart PLL with PLM = 1 */
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writel(0x00001236, base + MX5_PLL_DP_CTL);
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/* Wait for lock */
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while (!(readl(base + MX5_PLL_DP_CTL) & 1));
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/* Modify MFN value */
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writel(DP_MFN_800_DIT, base + MX5_PLL_DP_MFN);
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writel(DP_MFN_800_DIT, base + MX5_PLL_DP_HFS_MFN);
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/* Reload MFN value */
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writel(0x1, base + MX5_PLL_DP_CONFIG);
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while (readl(base + MX5_PLL_DP_CONFIG) & 1);
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/* Wait at least 4 us */
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for (i = 0; i < 100; i++);
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/* Enable auto-restart AREN bit */
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dp_config |= MX5_PLL_DP_CONFIG_AREN;
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writel(dp_config, base + MX5_PLL_DP_CONFIG);
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}
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void imx51_init_lowlevel(unsigned int cpufreq_mhz)
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{
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void __iomem *ccm = (void __iomem *)MX51_CCM_BASE_ADDR;
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u32 r;
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int rev = imx51_silicon_revision();
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imx5_init_lowlevel();
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/* disable write combine for TO 2 and lower revs */
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if (rev < IMX_CHIP_REV_3_0) {
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__asm__ __volatile__("mrc 15, 1, %0, c9, c0, 1":"=r"(r));
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r |= (1 << 25);
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__asm__ __volatile__("mcr 15, 1, %0, c9, c0, 1" : : "r"(r));
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}
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/* Gate of clocks to the peripherals first */
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writel(0x3fffffff, ccm + MX5_CCM_CCGR0);
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writel(0x00000000, ccm + MX5_CCM_CCGR1);
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writel(0x00000000, ccm + MX5_CCM_CCGR2);
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writel(0x00000000, ccm + MX5_CCM_CCGR3);
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writel(0x00030000, ccm + MX5_CCM_CCGR4);
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writel(0x00fff030, ccm + MX5_CCM_CCGR5);
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writel(0x00000300, ccm + MX5_CCM_CCGR6);
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/* Disable IPU and HSC dividers */
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writel(0x00060000, ccm + MX5_CCM_CCDR);
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/* Make sure to switch the DDR away from PLL 1 */
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writel(0x19239145, ccm + MX5_CCM_CBCDR);
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/* make sure divider effective */
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while (readl(ccm + MX5_CCM_CDHIPR));
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/* Switch ARM to step clock */
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writel(0x4, ccm + MX5_CCM_CCSR);
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switch (cpufreq_mhz) {
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case 600:
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imx5_setup_pll_600((void __iomem *)MX51_PLL1_BASE_ADDR);
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break;
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default:
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/* Default maximum 800MHz */
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if (rev <= IMX_CHIP_REV_3_0)
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imx51_setup_pll800_bug();
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else
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imx5_setup_pll_800((void __iomem *)MX51_PLL1_BASE_ADDR);
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break;
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}
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imx5_setup_pll_665((void __iomem *)MX51_PLL3_BASE_ADDR);
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/* Switch peripheral to PLL 3 */
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writel(0x000010C0, ccm + MX5_CCM_CBCMR);
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writel(0x13239145, ccm + MX5_CCM_CBCDR);
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imx5_setup_pll_665((void __iomem *)MX51_PLL2_BASE_ADDR);
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/* Switch peripheral to PLL2 */
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writel(0x19239145, ccm + MX5_CCM_CBCDR);
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writel(0x000020C0, ccm + MX5_CCM_CBCMR);
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imx5_setup_pll_216((void __iomem *)MX51_PLL3_BASE_ADDR);
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/* Set the platform clock dividers */
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writel(0x00000125, MX51_ARM_BASE_ADDR + 0x14);
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/* Run at Full speed */
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writel(0x0, ccm + MX5_CCM_CACRR);
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/* Switch ARM back to PLL 1 */
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writel(0x0, ccm + MX5_CCM_CCSR);
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/* setup the rest */
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/* Use lp_apm (24MHz) source for perclk */
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writel(0x000020C2, ccm + MX5_CCM_CBCMR);
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/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
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writel(0x59239100, ccm + MX5_CCM_CBCDR);
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/* Restore the default values in the Gate registers */
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writel(0xffffffff, ccm + MX5_CCM_CCGR0);
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writel(0xffffffff, ccm + MX5_CCM_CCGR1);
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writel(0xffffffff, ccm + MX5_CCM_CCGR2);
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writel(0xffffffff, ccm + MX5_CCM_CCGR3);
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writel(0xffffffff, ccm + MX5_CCM_CCGR4);
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writel(0xffffffff, ccm + MX5_CCM_CCGR5);
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writel(0xffffffff, ccm + MX5_CCM_CCGR6);
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/* Use PLL 2 for UART's, get 66.5MHz from it */
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writel(0xA591A020, ccm + MX5_CCM_CSCMR1);
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writel(0x00C30321, ccm + MX5_CCM_CSCDR1);
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/* make sure divider effective */
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while (readl(ccm + MX5_CCM_CDHIPR));
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writel(0x0, ccm + MX5_CCM_CCDR);
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}
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