400 lines
22 KiB
C
400 lines
22 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDRAM_H_
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#define _SDRAM_H_
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/* Group: sdr.phygrp.sccgrp */
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#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
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/* Group: sdr.phygrp.phymgrgrp */
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#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
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/* Group: sdr.phygrp.rwmgrgrp */
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#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
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/* Group: sdr.phygrp.datamgrgrp */
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#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
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/* Group: sdr.phygrp.regfilegrp */
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#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
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/* Group: sdr.ctrlgrp */
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#define SDR_CTRLGRP_ADDRESS 0x5000
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/* Register: sdr.ctrlgrp.ctrlcfg */
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#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000
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/* Register: sdr.ctrlgrp.dramtiming1 */
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#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004
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/* Register: sdr.ctrlgrp.dramtiming2 */
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#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008
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/* Register: sdr.ctrlgrp.dramtiming3 */
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#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c
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/* Register: sdr.ctrlgrp.dramtiming4 */
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#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010
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/* Register: sdr.ctrlgrp.lowpwrtiming */
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#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014
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/* Register: sdr.ctrlgrp.dramodt */
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#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018
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/* Register: sdr.ctrlgrp.dramaddrw */
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#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c
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/* Register: sdr.ctrlgrp.dramifwidth */
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#define SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS 0x5030
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/* Register: sdr.ctrlgrp.dramdevwidth */
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#define SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS 0x5034
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/* Register: sdr.ctrlgrp.dramsts */
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#define SDR_CTRLGRP_DRAMSTS_ADDRESS 0x5038
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/* Register: sdr.ctrlgrp.dramintr */
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#define SDR_CTRLGRP_DRAMINTR_ADDRESS 0x503c
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/* Register: sdr.ctrlgrp.sbecount */
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#define SDR_CTRLGRP_SBECOUNT_ADDRESS 0x5040
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/* Register: sdr.ctrlgrp.dbecount */
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#define SDR_CTRLGRP_DBECOUNT_ADDRESS 0x5044
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/* Register: sdr.ctrlgrp.erraddr */
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#define SDR_CTRLGRP_ERRADDR_ADDRESS 0x5048
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/* Register: sdr.ctrlgrp.dropcount */
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#define SDR_CTRLGRP_DROPCOUNT_ADDRESS 0x504c
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/* Register: sdr.ctrlgrp.dropaddr */
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#define SDR_CTRLGRP_DROPADDR_ADDRESS 0x5050
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/* Register: sdr.ctrlgrp.staticcfg */
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#define SDR_CTRLGRP_STATICCFG_ADDRESS 0x505c
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/* Register: sdr.ctrlgrp.ctrlwidth */
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#define SDR_CTRLGRP_CTRLWIDTH_ADDRESS 0x5060
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/* Register: sdr.ctrlgrp.cportwidth */
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#define SDR_CTRLGRP_CPORTWIDTH_ADDRESS 0x5064
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/* Register: sdr.ctrlgrp.cportwmap */
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#define SDR_CTRLGRP_CPORTWMAP_ADDRESS 0x5068
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/* Register: sdr.ctrlgrp.cportrmap */
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#define SDR_CTRLGRP_CPORTRMAP_ADDRESS 0x506c
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/* Register: sdr.ctrlgrp.rfifocmap */
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#define SDR_CTRLGRP_RFIFOCMAP_ADDRESS 0x5070
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/* Register: sdr.ctrlgrp.wfifocmap */
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#define SDR_CTRLGRP_WFIFOCMAP_ADDRESS 0x5074
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/* Register: sdr.ctrlgrp.cportrdwr */
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#define SDR_CTRLGRP_CPORTRDWR_ADDRESS 0x5078
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/* Register: sdr.ctrlgrp.portcfg */
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#define SDR_CTRLGRP_PORTCFG_ADDRESS 0x507c
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/* Register: sdr.ctrlgrp.fpgaportrst */
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#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
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/* Register: sdr.ctrlgrp.fifocfg */
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#define SDR_CTRLGRP_FIFOCFG_ADDRESS 0x5088
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/* Register: sdr.ctrlgrp.mppriority */
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#define SDR_CTRLGRP_MPPRIORITY_ADDRESS 0x50ac
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/* Wide Register: sdr.ctrlgrp.mpweight */
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#define SDR_CTRLGRP_MPWEIGHT_ADDRESS 0x50b0
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/* Register: sdr.ctrlgrp.mpweight.mpweight_0 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS 0x50b0
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/* Register: sdr.ctrlgrp.mpweight.mpweight_1 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS 0x50b4
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/* Register: sdr.ctrlgrp.mpweight.mpweight_2 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS 0x50b8
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/* Register: sdr.ctrlgrp.mpweight.mpweight_3 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS 0x50bc
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/* Register: sdr.ctrlgrp.mppacing.mppacing_0 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS 0x50c0
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/* Register: sdr.ctrlgrp.mppacing.mppacing_1 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS 0x50c4
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/* Register: sdr.ctrlgrp.mppacing.mppacing_2 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS 0x50c8
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/* Register: sdr.ctrlgrp.mppacing.mppacing_3 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS 0x50cc
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/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_0 */
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#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS 0x50d0
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/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_1 */
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#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS 0x50d4
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/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_2 */
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#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS 0x50d8
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/* Wide Register: sdr.ctrlgrp.phyctrl */
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#define SDR_CTRLGRP_PHYCTRL_ADDRESS 0x5150
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/* Register: sdr.ctrlgrp.phyctrl.phyctrl_0 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS 0x5150
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/* Register: sdr.ctrlgrp.phyctrl.phyctrl_1 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_ADDRESS 0x5154
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/* Register: sdr.ctrlgrp.phyctrl.phyctrl_2 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_ADDRESS 0x5158
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/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_0 */
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/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_0 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
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/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_1 */
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/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_1 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
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/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_2 */
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/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_2 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
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/* Register template: sdr::ctrlgrp::ctrlcfg */
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#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_LSB 26
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#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_MASK 0x04000000
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#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_LSB 25
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#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_MASK 0x02000000
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#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_LSB 24
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#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_MASK 0x01000000
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
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#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
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#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
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#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
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#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
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#define SDR_CTRLGRP_CTRLCFG_GENDBE_LSB 14
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#define SDR_CTRLGRP_CTRLCFG_GENDBE_MASK 0x00004000
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#define SDR_CTRLGRP_CTRLCFG_GENSBE_LSB 13
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#define SDR_CTRLGRP_CTRLCFG_GENSBE_MASK 0x00002000
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#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_LSB 12
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#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_MASK 0x00001000
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#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
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#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
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#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
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#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
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#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
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#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
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#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
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#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
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#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
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#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
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/* Register template: sdr::ctrlgrp::dramtiming1 */
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#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
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#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
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#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
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#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
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#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
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#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
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#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
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#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
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#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
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#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
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#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::dramtiming2 */
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#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
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#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
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#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
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#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
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#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
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#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
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#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
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#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
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#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
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/* Register template: sdr::ctrlgrp::dramtiming3 */
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#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
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#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
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#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
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#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
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#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
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#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
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#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
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#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
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#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::dramtiming4 */
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#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
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#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
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#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
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#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
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#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
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#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
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/* Register template: sdr::ctrlgrp::lowpwrtiming */
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#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
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#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
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#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
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#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
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/* Register template: sdr::ctrlgrp::dramaddrw */
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#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
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#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
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#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
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#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
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#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
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#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
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#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
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#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
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/* Register template: sdr::ctrlgrp::dramifwidth */
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#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
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#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
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/* Register template: sdr::ctrlgrp::dramdevwidth */
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#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
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#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::dramintr */
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#define SDR_CTRLGRP_DRAMINTR_INTRCLR_LSB 4
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#define SDR_CTRLGRP_DRAMINTR_INTRCLR_MASK 0x00000010
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#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_LSB 3
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#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_MASK 0x00000008
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#define SDR_CTRLGRP_DRAMINTR_DBEMASK_LSB 2
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#define SDR_CTRLGRP_DRAMINTR_DBEMASK_MASK 0x00000004
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#define SDR_CTRLGRP_DRAMINTR_SBEMASK_LSB 1
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#define SDR_CTRLGRP_DRAMINTR_SBEMASK_MASK 0x00000002
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#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
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#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
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/* Register template: sdr::ctrlgrp::sbecount */
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#define SDR_CTRLGRP_SBECOUNT_COUNT_LSB 0
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#define SDR_CTRLGRP_SBECOUNT_COUNT_MASK 0x000000ff
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/* Register template: sdr::ctrlgrp::dbecount */
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#define SDR_CTRLGRP_DBECOUNT_COUNT_LSB 0
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#define SDR_CTRLGRP_DBECOUNT_COUNT_MASK 0x000000ff
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/* Register template: sdr::ctrlgrp::staticcfg */
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#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
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#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
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#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
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#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
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#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
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#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
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/* Register template: sdr::ctrlgrp::ctrlwidth */
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#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
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#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
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/* Register template: sdr::ctrlgrp::cportwidth */
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#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
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#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
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/* Register template: sdr::ctrlgrp::cportwmap */
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#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
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#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
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/* Register template: sdr::ctrlgrp::cportrmap */
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#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
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#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
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/* Register template: sdr::ctrlgrp::rfifocmap */
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#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
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#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
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/* Register template: sdr::ctrlgrp::wfifocmap */
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#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
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#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
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/* Register template: sdr::ctrlgrp::cportrdwr */
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#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
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#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
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/* Register template: sdr::ctrlgrp::portcfg */
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#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
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#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
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#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
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#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
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/* Register template: sdr::ctrlgrp::fifocfg */
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#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
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#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
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#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
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#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
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/* Register template: sdr::ctrlgrp::mppriority */
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#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
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#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
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/* Wide Register template: sdr::ctrlgrp::mpweight */
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
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#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
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/* Wide Register template: sdr::ctrlgrp::mppacing */
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
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/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
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#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
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/* Wide Register template: sdr::ctrlgrp::mpthresholdrst */
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
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0xffffffff
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
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0xffffffff
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/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
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#define \
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SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
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0x0000ffff
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/* Register template: sdr::ctrlgrp::remappriority */
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#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
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#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
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/* Wide Register template: sdr::ctrlgrp::phyctrl */
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_MASK 0xfffff000
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
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(((x) << 12) & 0xfffff000)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_LSB 10
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_MASK 0x00000c00
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
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(((x) << 10) & 0x00000c00)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_LSB 9
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_MASK 0x00000200
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
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(((x) << 9) & 0x00000200)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_LSB 8
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_MASK 0x00000100
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
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(((x) << 8) & 0x00000100)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_LSB 6
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_MASK 0x000000c0
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
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(((x) << 6) & 0x000000c0)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_LSB 4
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_MASK 0x00000030
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
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(((x) << 4) & 0x00000030)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_LSB 2
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_MASK 0x0000000c
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
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(((x) << 2) & 0x0000000c)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_LSB 0
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_MASK 0x00000003
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
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(((x) << 0) & 0x00000003)
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_LSB 12
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_MASK 0xfffff000
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
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(((x) << 12) & 0xfffff000)
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_LSB 0
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_MASK 0x00000fff
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
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(((x) << 0) & 0x00000fff)
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/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_LSB 0
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_MASK 0x00000fff
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#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
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(((x) << 0) & 0x00000fff)
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/* Register template: sdr::ctrlgrp::dramodt */
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#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
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#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
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#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
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#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
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/* Register template: sdr::ctrlgrp::fpgaportrst */
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#define SDR_CTRLGRP_FPGAPORTRST_READ_PORT_0_LSB 0
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#define SDR_CTRLGRP_FPGAPORTRST_WRITE_PORT_0_LSB 4
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#define SDR_CTRLGRP_FPGAPORTRST_COMMAND_PORT_0_LSB 8
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/* Field instance: sdr::ctrlgrp::dramsts */
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#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
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#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
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#endif /* _SDRAM_H_ */
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