126 lines
2.7 KiB
C
126 lines
2.7 KiB
C
#ifndef __MACH_IMX6_H
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#define __MACH_IMX6_H
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#include <io.h>
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#include <mach/generic.h>
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#include <mach/imx6-regs.h>
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#include <mach/revision.h>
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void imx6_init_lowlevel(void);
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#define IMX6_ANATOP_SI_REV 0x260
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#define IMX6SL_ANATOP_SI_REV 0x280
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#define IMX6_CPUTYPE_IMX6SL 0x160
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#define IMX6_CPUTYPE_IMX6S 0x161
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#define IMX6_CPUTYPE_IMX6DL 0x261
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#define IMX6_CPUTYPE_IMX6SX 0x462
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#define IMX6_CPUTYPE_IMX6D 0x263
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#define IMX6_CPUTYPE_IMX6Q 0x463
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#define IMX6_CPUTYPE_IMX6UL 0x164
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#define SCU_CONFIG 0x04
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static inline int scu_get_core_count(void)
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{
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unsigned long base;
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unsigned int ncores;
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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ncores = readl(base + SCU_CONFIG);
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return (ncores & 0x03) + 1;
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}
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static inline int __imx6_cpu_type(void)
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{
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uint32_t val;
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val = readl(MX6_ANATOP_BASE_ADDR + IMX6_ANATOP_SI_REV);
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val = (val >> 16) & 0xff;
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/* non-MX6-standard SI_REV reg offset for MX6SL */
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if (IS_ENABLED(CONFIG_ARCH_IMX6SL) &&
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val < (IMX6_CPUTYPE_IMX6S & 0xff)) {
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uint32_t tmp;
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tmp = readl(MX6_ANATOP_BASE_ADDR + IMX6SL_ANATOP_SI_REV);
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tmp = (tmp >> 16) & 0xff;
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if ((IMX6_CPUTYPE_IMX6SL & 0xff) == tmp)
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/* intentionally skip scu_get_core_count() for MX6SL */
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return IMX6_CPUTYPE_IMX6SL;
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}
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val |= scu_get_core_count() << 8;
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return val;
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}
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static inline int imx6_cpu_type(void)
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{
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if (!cpu_is_mx6())
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return 0;
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return __imx6_cpu_type();
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}
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#define DEFINE_MX6_CPU_TYPE(str, type) \
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static inline int cpu_mx6_is_##str(void) \
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{ \
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return __imx6_cpu_type() == type; \
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} \
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\
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static inline int cpu_is_##str(void) \
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{ \
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if (!cpu_is_mx6()) \
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return 0; \
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return cpu_mx6_is_##str(); \
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}
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DEFINE_MX6_CPU_TYPE(mx6s, IMX6_CPUTYPE_IMX6S);
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DEFINE_MX6_CPU_TYPE(mx6dl, IMX6_CPUTYPE_IMX6DL);
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DEFINE_MX6_CPU_TYPE(mx6q, IMX6_CPUTYPE_IMX6Q);
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DEFINE_MX6_CPU_TYPE(mx6d, IMX6_CPUTYPE_IMX6D);
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DEFINE_MX6_CPU_TYPE(mx6sx, IMX6_CPUTYPE_IMX6SX);
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DEFINE_MX6_CPU_TYPE(mx6sl, IMX6_CPUTYPE_IMX6SL);
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DEFINE_MX6_CPU_TYPE(mx6ul, IMX6_CPUTYPE_IMX6UL);
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static inline int __imx6_cpu_revision(void)
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{
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uint32_t rev;
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uint32_t si_rev_offset = IMX6_ANATOP_SI_REV;
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if (IS_ENABLED(CONFIG_ARCH_IMX6SL) && cpu_mx6_is_mx6sl())
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si_rev_offset = IMX6SL_ANATOP_SI_REV;
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rev = readl(MX6_ANATOP_BASE_ADDR + si_rev_offset);
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switch (rev & 0xfff) {
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case 0x00:
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return IMX_CHIP_REV_1_0;
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case 0x01:
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return IMX_CHIP_REV_1_1;
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case 0x02:
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return IMX_CHIP_REV_1_2;
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case 0x03:
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return IMX_CHIP_REV_1_3;
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case 0x04:
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return IMX_CHIP_REV_1_4;
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case 0x05:
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return IMX_CHIP_REV_1_5;
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case 0x100:
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return IMX_CHIP_REV_2_0;
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}
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return IMX_CHIP_REV_UNKNOWN;
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}
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static inline int imx6_cpu_revision(void)
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{
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if (!cpu_is_mx6())
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return 0;
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return __imx6_cpu_revision();
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}
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#endif /* __MACH_IMX6_H */
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