165 lines
5.1 KiB
C
165 lines
5.1 KiB
C
/*
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* Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/imx31-regs.h>
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#include "clk.h"
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/* Register addresses */
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#define CCM_CCMR 0x00
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#define CCM_PDR0 0x04
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#define CCM_PDR1 0x08
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//#define CCM_RCSR 0x0C
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#define CCM_MPCTL 0x10
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#define CCM_UPCTL 0x14
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#define CCM_SRPCTL 0x18
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#define CCM_COSR 0x1C
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#define CCM_CGR0 0x20
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#define CCM_CGR1 0x24
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#define CCM_CGR2 0x28
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#define CCM_WIMR 0x2C
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#define CCM_LDC 0x30
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#define CCM_DCVR0 0x34
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#define CCM_DCVR1 0x38
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#define CCM_DCVR2 0x3C
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#define CCM_DCVR3 0x40
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#define CCM_LTR0 0x44
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#define CCM_LTR1 0x48
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#define CCM_LTR2 0x4C
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#define CCM_LTR3 0x50
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#define CCM_LTBR0 0x54
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#define CCM_LTBR1 0x58
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#define CCM_PMCR0 0x5C
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#define CCM_PMCR1 0x60
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#define CCM_PDR2 0x64
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enum mx31_clks {
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ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
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per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
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fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
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iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
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uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
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mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
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sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
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uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
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gacc_gate, emi_gate, rtic_gate, firi_gate, fpm, pll_ref, mpll_byp,
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clk_max
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};
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static struct clk *clks[clk_max];
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static const char *pll_ref_sel[] = {
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"dummy",
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"fpm",
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"ckih",
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"dummy",
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};
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static const char *mpll_byp_sel[] = {
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"mpll",
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"pll_ref",
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};
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static const char *mcu_main_sel[] = {
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"spll",
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"mpll_byp",
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};
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static const char *per_sel[] = {
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"per_div",
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"ipg",
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};
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static int imx31_ccm_probe(struct device_d *dev)
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{
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struct resource *iores;
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void __iomem *base;
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iores = dev_request_mem_resource(dev, 0);
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if (IS_ERR(iores))
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return PTR_ERR(iores);
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base = IOMEM(iores->start);
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writel(0xffffffff, base + CCM_CGR0);
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writel(0xffffffff, base + CCM_CGR1);
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writel(0xffffffff, base + CCM_CGR2);
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clks[ckih] = clk_fixed("ckih", 26000000);
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clks[ckil] = clk_fixed("ckil", 32768);
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clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
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clks[pll_ref] = imx_clk_mux("pll_ref", base + CCM_CCMR, 1, 2,
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pll_ref_sel, ARRAY_SIZE(pll_ref_sel));
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clks[mpll] = imx_clk_pllv1("mpll", "pll_ref", base + CCM_MPCTL);
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clks[spll] = imx_clk_pllv1("spll", "pll_ref", base + CCM_SRPCTL);
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clks[upll] = imx_clk_pllv1("upll", "pll_ref", base + CCM_UPCTL);
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clks[mpll_byp] = imx_clk_mux("mpll_byp", base + CCM_CCMR, 7, 1,
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mpll_byp_sel, ARRAY_SIZE(mpll_byp_sel));
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clks[mcu_main] = imx_clk_mux("mcu_main", base + CCM_PMCR0, 31, 1,
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mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
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clks[hsp] = imx_clk_divider("hsp", "mcu_main", base + CCM_PDR0, 11, 3);
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clks[ahb] = imx_clk_divider("ahb", "mcu_main", base + CCM_PDR0, 3, 3);
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clks[nfc] = imx_clk_divider("nfc", "ahb", base + CCM_PDR0, 8, 3);
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clks[ipg] = imx_clk_divider("ipg", "ahb", base + CCM_PDR0, 6, 2);
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clks[per_div] = imx_clk_divider("per_div", "upll", base + CCM_PDR0, 16, 5);
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clks[per] = imx_clk_mux("per", base + CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
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clkdev_add_physbase(clks[per], MX31_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_UART2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_UART3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_UART4_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_UART5_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_I2C1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_I2C2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_I2C3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX31_CSPI1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX31_CSPI2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[ipg], MX31_CSPI3_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_SDHC1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_SDHC2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per], MX31_GPT1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[hsp], MX31_IPU_CTRL_BASE_ADDR, NULL);
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return 0;
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}
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static __maybe_unused struct of_device_id imx31_ccm_dt_ids[] = {
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{
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.compatible = "fsl,imx31-ccm",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx31_ccm_driver = {
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.probe = imx31_ccm_probe,
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.name = "imx31-ccm",
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.of_compatible = DRV_OF_COMPAT(imx31_ccm_dt_ids),
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};
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static int imx31_ccm_init(void)
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{
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return platform_driver_register(&imx31_ccm_driver);
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}
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core_initcall(imx31_ccm_init);
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