The doxygen documentation is long outdated. Remove it. It will be replaced with sphinx based documentation later. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
446 lines
16 KiB
C
446 lines
16 KiB
C
#ifndef __INCLUDE_SPI_H
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#define __INCLUDE_SPI_H
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#include <driver.h>
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#include <linux/string.h>
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struct spi_board_info {
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char *name;
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int max_speed_hz;
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int bus_num;
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int chip_select;
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/* mode becomes spi_device.mode, and is essential for chips
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* where the default of SPI_CS_HIGH = 0 is wrong.
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*/
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u8 mode;
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u8 bits_per_word;
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void *platform_data;
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struct device_node *device_node;
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};
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/**
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* struct spi_device - Master side proxy for an SPI slave device
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* @dev: Driver model representation of the device.
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* @master: SPI controller used with the device.
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* @max_speed_hz: Maximum clock rate to be used with this chip
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* (on this board); may be changed by the device's driver.
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* The spi_transfer.speed_hz can override this for each transfer.
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* @chip_select: Chipselect, distinguishing chips handled by @master.
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* @mode: The spi mode defines how data is clocked out and in.
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* This may be changed by the device's driver.
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* The "active low" default for chipselect mode can be overridden
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* (by specifying SPI_CS_HIGH) as can the "MSB first" default for
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* each word in a transfer (by specifying SPI_LSB_FIRST).
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* @bits_per_word: Data transfers involve one or more words; word sizes
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* like eight or 12 bits are common. In-memory wordsizes are
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* powers of two bytes (e.g. 20 bit samples use 32 bits).
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* This may be changed by the device's driver, or left at the
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* default (0) indicating protocol words are eight bit bytes.
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* The spi_transfer.bits_per_word can override this for each transfer
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* (FIXME: not currently implemented).
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* @irq: Negative, or the number passed to request_irq() to receive
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* interrupts from this device.
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* @controller_state: Controller's runtime state
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* @controller_data: Board-specific definitions for controller, such as
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* FIFO initialization parameters; from board_info.controller_data
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* @modalias: Name of the driver to use with this device, or an alias
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* for that name. This appears in the sysfs "modalias" attribute
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* for driver coldplugging, and in uevents used for hotplugging
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*
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* A @spi_device is used to interchange data between an SPI slave
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* (usually a discrete chip) and CPU memory.
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*
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* In @dev, the platform_data is used to hold information about this
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* device that's meaningful to the device's protocol driver, but not
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* to its controller. One example might be an identifier for a chip
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* variant with slightly different functionality; another might be
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* information about how this particular board wires the chip's pins.
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*/
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struct spi_device {
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struct device_d dev;
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struct spi_master *master;
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u32 max_speed_hz;
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u8 chip_select;
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u8 mode;
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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#define SPI_MODE_0 (0|0) /* (original MicroWire) */
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#define SPI_MODE_1 (0|SPI_CPHA)
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#define SPI_MODE_2 (SPI_CPOL|0)
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#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
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#define SPI_CS_HIGH 0x04 /* chipselect active high? */
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#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
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#define SPI_3WIRE 0x10 /* SI/SO signals shared */
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#define SPI_LOOP 0x20 /* loopback mode */
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u8 bits_per_word;
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int irq;
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void *controller_state;
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void *controller_data;
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const char *modalias;
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/*
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* likely need more hooks for more protocol options affecting how
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* the controller talks to each chip, like:
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* - memory packing (12 bit samples into low bits, others zeroed)
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* - priority
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* - drop chipselect after each word
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* - chipselect delays
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* - ...
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*/
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};
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struct spi_message;
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/**
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* struct spi_master - interface to SPI master controller
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* @dev: device interface to this driver
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* @bus_num: board-specific (and often SOC-specific) identifier for a
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* given SPI controller.
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* @num_chipselect: chipselects are used to distinguish individual
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* SPI slaves, and are numbered from zero to num_chipselects.
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* each slave has a chipselect signal, but it's common that not
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* every chipselect is connected to a slave.
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* @setup: updates the device mode and clocking records used by a
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* device's SPI controller; protocol code may call this. This
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* must fail if an unrecognized or unsupported mode is requested.
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* It's always safe to call this unless transfers are pending on
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* the device whose settings are being modified.
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* @transfer: adds a message to the controller's transfer queue.
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* @cleanup: frees controller-specific state
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*
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* Each SPI master controller can communicate with one or more @spi_device
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* children. These make a small bus, sharing MOSI, MISO and SCK signals
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* but not chip select signals. Each device may be configured to use a
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* different clock rate, since those shared signals are ignored unless
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* the chip is selected.
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*
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* The driver for an SPI controller manages access to those devices through
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* a queue of spi_message transactions, copying data between CPU memory and
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* an SPI slave device. For each such message it queues, it calls the
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* message's completion function when the transaction completes.
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*/
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struct spi_master {
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struct device_d *dev;
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/* other than negative (== assign one dynamically), bus_num is fully
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* board-specific. usually that simplifies to being SOC-specific.
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* example: one SOC has three SPI controllers, numbered 0..2,
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* and one board's schematics might show it using SPI-2. software
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* would normally use bus_num=2 for that controller.
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*/
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s16 bus_num;
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/* chipselects will be integral to many controllers; some others
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* might use board-specific GPIOs.
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*/
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u16 num_chipselect;
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/* setup mode and clock, etc (spi driver may call many times) */
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int (*setup)(struct spi_device *spi);
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/* bidirectional bulk transfers
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*
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* + The transfer() method may not sleep; its main role is
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* just to add the message to the queue.
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* + For now there's no remove-from-queue operation, or
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* any other request management
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* + To a given spi_device, message queueing is pure fifo
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*
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* + The master's main job is to process its message queue,
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* selecting a chip then transferring data
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* + If there are multiple spi_device children, the i/o queue
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* arbitration algorithm is unspecified (round robin, fifo,
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* priority, reservations, preemption, etc)
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*
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* + Chipselect stays active during the entire message
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* (unless modified by spi_transfer.cs_change != 0).
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* + The message transfers use clock and SPI mode parameters
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* previously established by setup() for this device
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*/
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int (*transfer)(struct spi_device *spi,
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struct spi_message *mesg);
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/* called on release() to free memory provided by spi_master */
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void (*cleanup)(struct spi_device *spi);
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struct list_head list;
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};
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/*---------------------------------------------------------------------------*/
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/*
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* I/O INTERFACE between SPI controller and protocol drivers
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*
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* Protocol drivers use a queue of spi_messages, each transferring data
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* between the controller and memory buffers.
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*
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* The spi_messages themselves consist of a series of read+write transfer
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* segments. Those segments always read the same number of bits as they
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* write; but one or the other is easily ignored by passing a null buffer
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* pointer. (This is unlike most types of I/O API, because SPI hardware
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* is full duplex.)
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*
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* NOTE: Allocation of spi_transfer and spi_message memory is entirely
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* up to the protocol driver, which guarantees the integrity of both (as
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* well as the data buffers) for as long as the message is queued.
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*/
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/**
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* struct spi_transfer - a read/write buffer pair
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* @tx_buf: data to be written (dma-safe memory), or NULL
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* @rx_buf: data to be read (dma-safe memory), or NULL
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* @len: size of rx and tx buffers (in bytes)
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* @speed_hz: Select a speed other then the device default for this
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* transfer. If 0 the default (from @spi_device) is used.
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* @bits_per_word: select a bits_per_word other then the device default
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* for this transfer. If 0 the default (from @spi_device) is used.
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* @cs_change: affects chipselect after this transfer completes
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* @delay_usecs: microseconds to delay after this transfer before
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* (optionally) changing the chipselect status, then starting
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* the next transfer or completing this @spi_message.
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* @transfer_list: transfers are sequenced through @spi_message.transfers
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*
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* SPI transfers always write the same number of bytes as they read.
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* Protocol drivers should always provide @rx_buf and/or @tx_buf.
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*
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* If the transmit buffer is null, zeroes will be shifted out
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* while filling @rx_buf. If the receive buffer is null, the data
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* shifted in will be discarded. Only "len" bytes shift out (or in).
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* It's an error to try to shift out a partial word. (For example, by
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* shifting out three bytes with word size of sixteen or twenty bits;
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* the former uses two bytes per word, the latter uses four bytes.)
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*
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* In-memory data values are always in native CPU byte order, translated
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* from the wire byte order (big-endian except with SPI_LSB_FIRST). So
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* for example when bits_per_word is sixteen, buffers are 2N bytes long
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* (@len = 2N) and hold N sixteen bit words in CPU byte order.
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*
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* When the word size of the SPI transfer is not a power-of-two multiple
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* of eight bits, those in-memory words include extra bits. In-memory
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* words are always seen by protocol drivers as right-justified, so the
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* undefined (rx) or unused (tx) bits are always the most significant bits.
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*
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* All SPI transfers start with the relevant chipselect active. Normally
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* it stays selected until after the last transfer in a message. Drivers
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* can affect the chipselect signal using cs_change.
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*
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* (i) If the transfer isn't the last one in the message, this flag is
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* used to make the chipselect briefly go inactive in the middle of the
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* message. Toggling chipselect in this way may be needed to terminate
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* a chip command, letting a single spi_message perform all of group of
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* chip transactions together.
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*
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* (ii) When the transfer is the last one in the message, the chip may
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* stay selected until the next transfer. On multi-device SPI busses
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* with nothing blocking messages going to other devices, this is just
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* a performance hint; starting a message to another device deselects
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* this one. But in other cases, this can be used to ensure correctness.
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* Some devices need protocol transactions to be built from a series of
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* spi_message submissions, where the content of one message is determined
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* by the results of previous messages and where the whole transaction
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* ends when the chipselect goes intactive.
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*
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* The code that submits an spi_message (and its spi_transfers)
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* to the lower layers is responsible for managing its memory.
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* Zero-initialize every field you don't set up explicitly, to
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* insulate against future API updates. After you submit a message
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* and its transfers, ignore them until its completion callback.
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*/
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struct spi_transfer {
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/* it's ok if tx_buf == rx_buf (right?)
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* for MicroWire, one buffer must be null
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* buffers must work with dma_*map_single() calls, unless
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* spi_message.is_dma_mapped reports a pre-existing mapping
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*/
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const void *tx_buf;
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void *rx_buf;
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unsigned len;
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unsigned cs_change:1;
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u8 bits_per_word;
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u16 delay_usecs;
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u32 speed_hz;
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struct list_head transfer_list;
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};
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/**
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* struct spi_message - one multi-segment SPI transaction
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* @transfers: list of transfer segments in this transaction
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* @spi: SPI device to which the transaction is queued
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* @actual_length: the total number of bytes that were transferred in all
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* successful segments
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* @status: zero for success, else negative errno
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* @queue: for use by whichever driver currently owns the message
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* @state: for use by whichever driver currently owns the message
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*
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* A @spi_message is used to execute an atomic sequence of data transfers,
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* each represented by a struct spi_transfer. The sequence is "atomic"
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* in the sense that no other spi_message may use that SPI bus until that
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* sequence completes. On some systems, many such sequences can execute as
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* as single programmed DMA transfer. On all systems, these messages are
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* queued, and might complete after transactions to other devices. Messages
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* sent to a given spi_device are alway executed in FIFO order.
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*
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* The code that submits an spi_message (and its spi_transfers)
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* to the lower layers is responsible for managing its memory.
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* Zero-initialize every field you don't set up explicitly, to
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* insulate against future API updates. After you submit a message
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* and its transfers, ignore them until its completion callback.
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*/
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struct spi_message {
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struct list_head transfers;
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struct spi_device *spi;
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/* REVISIT: we might want a flag affecting the behavior of the
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* last transfer ... allowing things like "read 16 bit length L"
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* immediately followed by "read L bytes". Basically imposing
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* a specific message scheduling algorithm.
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*
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* Some controller drivers (message-at-a-time queue processing)
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* could provide that as their default scheduling algorithm. But
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* others (with multi-message pipelines) could need a flag to
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* tell them about such special cases.
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*/
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unsigned actual_length;
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int status;
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/* for optional use by whatever driver currently owns the
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* spi_message ... between calls to spi_async and then later
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* complete(), that's the spi_master controller driver.
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*/
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struct list_head queue;
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void *state;
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};
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static inline void spi_message_init(struct spi_message *m)
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{
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memset(m, 0, sizeof *m);
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INIT_LIST_HEAD(&m->transfers);
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}
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static inline void
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spi_message_add_tail(struct spi_transfer *t, struct spi_message *m)
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{
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list_add_tail(&t->transfer_list, &m->transfers);
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}
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static inline void
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spi_transfer_del(struct spi_transfer *t)
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{
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list_del(&t->transfer_list);
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}
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/* All these synchronous SPI transfer routines are utilities layered
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* over the core async transfer primitive. Here, "synchronous" means
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* they will sleep uninterruptibly until the async transfer completes.
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*/
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int spi_sync(struct spi_device *spi, struct spi_message *message);
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struct spi_device *spi_new_device(struct spi_master *master,
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struct spi_board_info *chip);
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int spi_register_master(struct spi_master *master);
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#ifdef CONFIG_SPI
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int spi_register_board_info(struct spi_board_info const *info, int num);
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#else
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static inline int spi_register_board_info(struct spi_board_info const *info,
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int num)
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{
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return 0;
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}
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#endif
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/**
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* spi_write - SPI synchronous write
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* @spi: device to which data will be written
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* @buf: data buffer
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* @len: data buffer size
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* Context: can sleep
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*
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* This writes the buffer and returns zero or a negative error code.
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* Callable only from contexts that can sleep.
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*/
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static inline int
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spi_write(struct spi_device *spi, const void *buf, size_t len)
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{
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struct spi_transfer t = {
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.tx_buf = buf,
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.len = len,
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};
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struct spi_message m;
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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return spi_sync(spi, &m);
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}
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/**
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* spi_read - SPI synchronous read
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* @spi: device from which data will be read
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* @buf: data buffer
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* @len: data buffer size
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* Context: can sleep
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*
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* This reads the buffer and returns zero or a negative error code.
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* Callable only from contexts that can sleep.
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*/
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static inline int
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spi_read(struct spi_device *spi, void *buf, size_t len)
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{
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struct spi_transfer t = {
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.rx_buf = buf,
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.len = len,
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};
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struct spi_message m;
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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return spi_sync(spi, &m);
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}
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/* this copies txbuf and rxbuf data; for small transfers only! */
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extern int spi_write_then_read(struct spi_device *spi,
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const void *txbuf, unsigned n_tx,
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void *rxbuf, unsigned n_rx);
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/**
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* spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
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* @spi: device with which data will be exchanged
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* @cmd: command to be written before data is read back
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* Context: can sleep
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*
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* This returns the (unsigned) eight bit number returned by the
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* device, or else a negative error code. Callable only from
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* contexts that can sleep.
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*/
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static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
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{
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ssize_t status;
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u8 result;
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status = spi_write_then_read(spi, &cmd, 1, &result, 1);
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/* return negative errno or unsigned value */
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return (status < 0) ? status : result;
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}
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extern struct bus_type spi_bus;
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struct spi_master *spi_get_master(int bus);
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static inline int spi_driver_register(struct driver_d *drv)
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{
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drv->bus = &spi_bus;
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return register_driver(drv);
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}
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#define device_spi_driver(drv) \
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register_driver_macro(device,spi,drv)
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#endif /* __INCLUDE_SPI_H */
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