115 lines
3.4 KiB
C
115 lines
3.4 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (c) 2014 EPFL, Philippe Rétornaz <philippe.retornaz@epfl.ch>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm.h>
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#include <asm/system.h>
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#include <asm-generic/memory_layout.h>
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#include <asm-generic/sections.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/imx31-regs.h>
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#include <mach/imx-pll.h>
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#include <asm/barebox-arm-head.h>
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#include <mach/esdctl.h>
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static noinline __noreturn void mx31moboard_startup(void)
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{
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uint32_t r;
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volatile int c;
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/* Enable IPU Display interface */
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writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
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writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
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for (c = 0; c < 0x4000; c++) ;
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writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR +
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MX31_CCM_CCMR);
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writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS,
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MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
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writel(MX31_PDR0_CSI_PODF(0x1ff) | \
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MX31_PDR0_PER_PODF(7) | \
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MX31_PDR0_HSP_PODF(3) | \
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MX31_PDR0_NFC_PODF(5) | \
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MX31_PDR0_IPG_PODF(1) | \
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MX31_PDR0_MAX_PODF(3) | \
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MX31_PDR0_MCU_PODF(0), \
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MX31_CCM_BASE_ADDR + MX31_CCM_PDR0);
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writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0x33) |
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IMX_PLL_MFI(0xa) | IMX_PLL_MFN(0x0C),
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MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL);
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writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) |
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IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR +
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MX31_CCM_SPCTL);
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/*
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* Configure IOMUXC
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* Clears 0x43fa_c26c - 0x43fa_c2dc with 0,
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* except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000)
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* and 0x43fa_c280 (untouched)
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* (behaviour copied by sha, source unknown)
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*/
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writel(0, 0x43fac26c); /* SDCLK */
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writel(0, 0x43fac270); /* CAS */
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writel(0, 0x43fac274); /* RAS */
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writel(0x1000, 0x43fac27c); /* CSD0 */
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/* DQM3, DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 */
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for (r = 0x43fac284; r <= 0x43fac2dc; r += 4)
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writel(0, r);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0xa0000000)
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imx31_barebox_entry(0);
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writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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writel(0x00695727, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0);
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writel(0x92100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00);
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writel(0xa2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0x12344321, MX31_CSD0_BASE_ADDR);
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writel(0x12344321, MX31_CSD0_BASE_ADDR);
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writel(0xb2100000, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33);
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writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000);
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writel(0x82226080, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
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writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR);
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writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
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imx31_barebox_entry(0);
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}
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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arm_cpu_lowlevel_init();
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/* Temporary stack location in internal SRAM */
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arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8);
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mx31moboard_startup();
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}
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