156 lines
7.3 KiB
C
156 lines
7.3 KiB
C
/*
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* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
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* See file CREDITS for list of people who contributed to this project.
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*
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* This file is part of barebox.
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*
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* barebox is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* barebox is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with barebox. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @file
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* Register and bit definitions for the MCF548X and MCF547x
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* DMA Serial Peripheral Interface (DSPI)
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*/
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#ifndef __MCF548X_DSPI_H__
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#define __MCF548X_DSPI_H__
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/*
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* DMA Serial Peripheral Interface (DSPI)
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*/
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/* Register read/write macros */
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#define MCF_DSPI_DMCR (*(vuint32_t*)(&__MBAR[0x008A00]))
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#define MCF_DSPI_DTCR (*(vuint32_t*)(&__MBAR[0x008A08]))
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#define MCF_DSPI_DCTAR0 (*(vuint32_t*)(&__MBAR[0x008A0C]))
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#define MCF_DSPI_DCTAR1 (*(vuint32_t*)(&__MBAR[0x008A10]))
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#define MCF_DSPI_DCTAR2 (*(vuint32_t*)(&__MBAR[0x008A14]))
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#define MCF_DSPI_DCTAR3 (*(vuint32_t*)(&__MBAR[0x008A18]))
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#define MCF_DSPI_DCTAR4 (*(vuint32_t*)(&__MBAR[0x008A1C]))
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#define MCF_DSPI_DCTAR5 (*(vuint32_t*)(&__MBAR[0x008A20]))
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#define MCF_DSPI_DCTAR6 (*(vuint32_t*)(&__MBAR[0x008A24]))
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#define MCF_DSPI_DCTAR7 (*(vuint32_t*)(&__MBAR[0x008A28]))
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#define MCF_DSPI_DCTARn(x) (*(vuint32_t*)(&__MBAR[0x008A0C+((x)*0x004)]))
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#define MCF_DSPI_DSR (*(vuint32_t*)(&__MBAR[0x008A2C]))
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#define MCF_DSPI_DIRSR (*(vuint32_t*)(&__MBAR[0x008A30]))
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#define MCF_DSPI_DTFR (*(vuint32_t*)(&__MBAR[0x008A34]))
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#define MCF_DSPI_DRFR (*(vuint32_t*)(&__MBAR[0x008A38]))
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#define MCF_DSPI_DTFDR0 (*(vuint32_t*)(&__MBAR[0x008A3C]))
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#define MCF_DSPI_DTFDR1 (*(vuint32_t*)(&__MBAR[0x008A40]))
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#define MCF_DSPI_DTFDR2 (*(vuint32_t*)(&__MBAR[0x008A44]))
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#define MCF_DSPI_DTFDR3 (*(vuint32_t*)(&__MBAR[0x008A48]))
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#define MCF_DSPI_DTFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A3C+((x)*0x004)]))
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#define MCF_DSPI_DRFDR0 (*(vuint32_t*)(&__MBAR[0x008A7C]))
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#define MCF_DSPI_DRFDR1 (*(vuint32_t*)(&__MBAR[0x008A80]))
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#define MCF_DSPI_DRFDR2 (*(vuint32_t*)(&__MBAR[0x008A84]))
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#define MCF_DSPI_DRFDR3 (*(vuint32_t*)(&__MBAR[0x008A88]))
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#define MCF_DSPI_DRFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A7C+((x)*0x004)]))
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/* Bit definitions and macros for MCF_DSPI_DMCR */
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#define MCF_DSPI_DMCR_HALT (0x00000001)
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#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
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#define MCF_DSPI_DMCR_CRXF (0x00000400)
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#define MCF_DSPI_DMCR_CTXF (0x00000800)
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#define MCF_DSPI_DMCR_DRXF (0x00001000)
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#define MCF_DSPI_DMCR_DTXF (0x00002000)
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#define MCF_DSPI_DMCR_CSIS0 (0x00010000)
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#define MCF_DSPI_DMCR_CSIS2 (0x00040000)
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#define MCF_DSPI_DMCR_CSIS3 (0x00080000)
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#define MCF_DSPI_DMCR_CSIS5 (0x00200000)
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#define MCF_DSPI_DMCR_ROOE (0x01000000)
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#define MCF_DSPI_DMCR_PCSSE (0x02000000)
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#define MCF_DSPI_DMCR_MTFE (0x04000000)
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#define MCF_DSPI_DMCR_FRZ (0x08000000)
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#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
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#define MCF_DSPI_DMCR_CSCK (0x40000000)
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#define MCF_DSPI_DMCR_MSTR (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DTCR */
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#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_DSPI_DCTARn */
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#define MCF_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0)
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#define MCF_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4)
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#define MCF_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8)
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#define MCF_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12)
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#define MCF_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16)
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#define MCF_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18)
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#define MCF_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20)
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#define MCF_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22)
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#define MCF_DSPI_DCTARn_LSBFE (0x01000000)
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#define MCF_DSPI_DCTARn_CPHA (0x02000000)
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#define MCF_DSPI_DCTARn_CPOL (0x04000000)
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#define MCF_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27)
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#define MCF_DSPI_DCTARn_PCSSCK_1CLK (0x00000000)
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#define MCF_DSPI_DCTARn_PCSSCK_3CLK (0x00400000)
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#define MCF_DSPI_DCTARn_PCSSCK_5CLK (0x00800000)
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#define MCF_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000)
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#define MCF_DSPI_DCTARn_PASC_1CLK (0x00000000)
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#define MCF_DSPI_DCTARn_PASC_3CLK (0x00100000)
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#define MCF_DSPI_DCTARn_PASC_5CLK (0x00200000)
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#define MCF_DSPI_DCTARn_PASC_7CLK (0x00300000)
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#define MCF_DSPI_DCTARn_PDT_1CLK (0x00000000)
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#define MCF_DSPI_DCTARn_PDT_3CLK (0x00040000)
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#define MCF_DSPI_DCTARn_PDT_5CLK (0x00080000)
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#define MCF_DSPI_DCTARn_PDT_7CLK (0x000A0000)
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#define MCF_DSPI_DCTARn_PBR_1CLK (0x00000000)
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#define MCF_DSPI_DCTARn_PBR_3CLK (0x00010000)
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#define MCF_DSPI_DCTARn_PBR_5CLK (0x00020000)
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#define MCF_DSPI_DCTARn_PBR_7CLK (0x00030000)
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/* Bit definitions and macros for MCF_DSPI_DSR */
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#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0)
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#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
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#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
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#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
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#define MCF_DSPI_DSR_RFDF (0x00020000)
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#define MCF_DSPI_DSR_RFOF (0x00080000)
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#define MCF_DSPI_DSR_TFFF (0x02000000)
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#define MCF_DSPI_DSR_TFUF (0x08000000)
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#define MCF_DSPI_DSR_EOQF (0x10000000)
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#define MCF_DSPI_DSR_TXRXS (0x40000000)
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#define MCF_DSPI_DSR_TCF (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DIRSR */
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#define MCF_DSPI_DIRSR_RFDFS (0x00010000)
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#define MCF_DSPI_DIRSR_RFDFE (0x00020000)
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#define MCF_DSPI_DIRSR_RFOFE (0x00080000)
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#define MCF_DSPI_DIRSR_TFFFS (0x01000000)
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#define MCF_DSPI_DIRSR_TFFFE (0x02000000)
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#define MCF_DSPI_DIRSR_TFUFE (0x08000000)
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#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
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#define MCF_DSPI_DIRSR_TCFE (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DTFR */
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#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0)
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#define MCF_DSPI_DTFR_CS0 (0x00010000)
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#define MCF_DSPI_DTFR_CS2 (0x00040000)
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#define MCF_DSPI_DTFR_CS3 (0x00080000)
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#define MCF_DSPI_DTFR_CS5 (0x00200000)
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#define MCF_DSPI_DTFR_CTCNT (0x04000000)
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#define MCF_DSPI_DTFR_EOQ (0x08000000)
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#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
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#define MCF_DSPI_DTFR_CONT (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DRFR */
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#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0)
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/* Bit definitions and macros for MCF_DSPI_DTFDRn */
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#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0)
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#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_DSPI_DRFDRn */
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#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0)
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#endif /* __MCF548X_DSPI_H__ */
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