110 lines
5.1 KiB
C
110 lines
5.1 KiB
C
/*
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* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
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* See file CREDITS for list of people who contributed to this project.
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*
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* This file is part of barebox.
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*
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* barebox is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* barebox is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with barebox. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @file
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* Register and bit definitions for the MCF548X and MCF547x
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* SDRAM Controller (SDRAMC)
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*/
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#ifndef __MCF548X_SDRAMC_H__
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#define __MCF548X_SDRAMC_H__
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/*
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* SDRAM Controller (SDRAMC)
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*/
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/* Register read/write macros */
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#define MCF_SDRAMC_SDRAMDS (*(vuint32_t*)(&__MBAR[0x000004]))
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#define MCF_SDRAMC_CS0CFG (*(vuint32_t*)(&__MBAR[0x000020]))
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#define MCF_SDRAMC_CS1CFG (*(vuint32_t*)(&__MBAR[0x000024]))
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#define MCF_SDRAMC_CS2CFG (*(vuint32_t*)(&__MBAR[0x000028]))
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#define MCF_SDRAMC_CS3CFG (*(vuint32_t*)(&__MBAR[0x00002C]))
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#define MCF_SDRAMC_CSnCFG(x) (*(vuint32_t*)(&__MBAR[0x000020+((x)*0x004)]))
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#define MCF_SDRAMC_SDMR (*(vuint32_t*)(&__MBAR[0x000100]))
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#define MCF_SDRAMC_SDCR (*(vuint32_t*)(&__MBAR[0x000104]))
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#define MCF_SDRAMC_SDCFG1 (*(vuint32_t*)(&__MBAR[0x000108]))
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#define MCF_SDRAMC_SDCFG2 (*(vuint32_t*)(&__MBAR[0x00010C]))
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/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
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#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0)
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#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2)
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#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4)
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#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6)
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#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8)
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#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x02)
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#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x01)
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#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0x00)
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#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x03)
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/* Bit definitions and macros for MCF_SDRAMC_CSnCFG */
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#define MCF_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0)
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#define MCF_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20)
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#define MCF_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000)
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#define MCF_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013)
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#define MCF_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014)
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#define MCF_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015)
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#define MCF_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016)
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#define MCF_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017)
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#define MCF_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018)
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#define MCF_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019)
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#define MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A)
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#define MCF_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B)
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#define MCF_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C)
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#define MCF_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D)
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#define MCF_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E)
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#define MCF_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F)
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/* Bit definitions and macros for MCF_SDRAMC_SDMR */
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#define MCF_SDRAMC_SDMR_CMD (0x00010000)
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#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18)
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#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30)
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#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000)
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#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000)
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/* Bit definitions and macros for MCF_SDRAMC_SDCR */
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#define MCF_SDRAMC_SDCR_IPALL (0x00000002)
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#define MCF_SDRAMC_SDCR_IREF (0x00000004)
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#define MCF_SDRAMC_SDCR_BUFF (0x00000010)
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#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8)
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#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16)
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#define MCF_SDRAMC_SDCR_DRIVE (0x00400000)
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#define MCF_SDRAMC_SDCR_AP (0x00800000)
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#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24)
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#define MCF_SDRAMC_SDCR_REF (0x10000000)
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#define MCF_SDRAMC_SDCR_DDR (0x20000000)
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#define MCF_SDRAMC_SDCR_CKE (0x40000000)
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#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
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/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
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#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4)
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#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
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#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
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#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
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#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20)
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#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24)
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#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28)
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/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
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#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
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#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20)
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#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24)
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#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28)
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#endif /* __MCF548X_SDRAMC_H__ */
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