67 lines
2.7 KiB
C
67 lines
2.7 KiB
C
/*
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* Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de>
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* See file CREDITS for list of people who contributed to this project.
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*
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* This file is part of barebox.
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*
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* barebox is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* barebox is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with barebox. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @file
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* Register and bit definitions for the MCF548X and MCF547x
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* 32KByte System SRAM (SRAM)
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*/
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#ifndef __MCF548X_SRAM_H__
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#define __MCF548X_SRAM_H__
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/*
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* 32KByte System SRAM (SRAM)
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*/
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/* Register read/write macros */
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#define MCF_SRAM_SSCR (*(vuint32_t*)(&__MBAR[0x01FFC0]))
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#define MCF_SRAM_TCCR (*(vuint32_t*)(&__MBAR[0x01FFC4]))
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#define MCF_SRAM_TCCRDR (*(vuint32_t*)(&__MBAR[0x01FFC8]))
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#define MCF_SRAM_TCCRDW (*(vuint32_t*)(&__MBAR[0x01FFCC]))
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#define MCF_SRAM_TCCRSEC (*(vuint32_t*)(&__MBAR[0x01FFD0]))
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/* Bit definitions and macros for MCF_SRAM_SSCR */
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#define MCF_SRAM_SSCR_INLV (0x00010000)
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/* Bit definitions and macros for MCF_SRAM_TCCR */
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#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0)
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#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8)
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#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16)
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#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24)
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/* Bit definitions and macros for MCF_SRAM_TCCRDR */
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#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0)
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#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8)
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#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16)
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#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24)
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/* Bit definitions and macros for MCF_SRAM_TCCRDW */
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#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0)
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#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8)
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#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16)
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#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24)
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/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
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#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0)
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#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8)
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#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16)
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#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24)
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#endif /* __MCF548X_SRAM_H__ */
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