380 lines
12 KiB
C
380 lines
12 KiB
C
/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* Based on the Linux Tegra clock code
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/lowlevel.h>
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#include <mach/tegra20-car.h>
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#include "clk.h"
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static void __iomem *car_base;
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enum tegra20_clks {
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cpu, ac97 = 3, rtc, timer, uarta, uartb, gpio, sdmmc2, i2s1 = 11, i2c1,
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ndflash, sdmmc1, sdmmc4, twc, pwm, i2s2, epp, gr2d = 21, usbd, isp,
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gr3d, ide, disp2, disp1, host1x, vcp, cache2 = 31, mem, ahbdma, apbdma,
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kbc = 36, stat_mon, pmc, fuse, kfuse, sbc1, nor, spi, sbc2, xio, sbc3,
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dvc, dsi, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
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usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
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pex, owr, afi, csite, pcie_xclk, avpucq = 75, la, irama = 84, iramb,
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iramc, iramd, cram2, audio_2x, clk_d, csus = 92, cdev2, cdev1,
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vfir = 96, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
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osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
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pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
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pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
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pll_x, audio, pll_ref, twd, clk_max,
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};
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static struct clk *clks[clk_max];
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static struct clk_onecell_data clk_data;
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static unsigned int get_pll_ref_div(void)
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{
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u32 osc_ctrl = readl(car_base + CRC_OSC_CTRL);
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return 1U << ((osc_ctrl & CRC_OSC_CTRL_PLL_REF_DIV_MASK) >>
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CRC_OSC_CTRL_PLL_REF_DIV_SHIFT);
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}
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static void tegra20_osc_clk_init(void)
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{
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clks[clk_m] = clk_fixed("clk_m", tegra_get_osc_clock());
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clks[clk_32k] = clk_fixed("clk_32k", 32768);
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clks[pll_ref] = clk_fixed_factor("pll_ref", "clk_m", 1,
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get_pll_ref_div());
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}
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/* PLL frequency tables */
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static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
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{ 12000000, 600000000, 600, 12, 1, 8 },
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{ 13000000, 600000000, 600, 13, 1, 8 },
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{ 19200000, 600000000, 500, 16, 1, 6 },
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{ 26000000, 600000000, 600, 26, 1, 8 },
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
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{ 12000000, 216000000, 432, 12, 2, 8},
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{ 13000000, 216000000, 432, 13, 2, 8},
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{ 19200000, 216000000, 90, 4, 2, 1},
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{ 26000000, 216000000, 432, 26, 2, 8},
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
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{ 12000000, 666000000, 666, 12, 1, 8},
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{ 13000000, 666000000, 666, 13, 1, 8},
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{ 19200000, 666000000, 555, 16, 1, 8},
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{ 26000000, 666000000, 666, 26, 1, 8},
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{ 12000000, 600000000, 600, 12, 1, 8},
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{ 13000000, 600000000, 600, 13, 1, 8},
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{ 19200000, 600000000, 375, 12, 1, 6},
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{ 26000000, 600000000, 600, 26, 1, 8},
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
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/* 1 GHz */
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{ 12000000, 1000000000, 1000, 12, 1, 12},
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{ 13000000, 1000000000, 1000, 13, 1, 12},
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{ 19200000, 1000000000, 625, 12, 1, 8},
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{ 26000000, 1000000000, 1000, 26, 1, 12},
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/* 912 MHz */
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{ 12000000, 912000000, 912, 12, 1, 12},
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{ 13000000, 912000000, 912, 13, 1, 12},
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{ 19200000, 912000000, 760, 16, 1, 8},
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{ 26000000, 912000000, 912, 26, 1, 12},
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/* 816 MHz */
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{ 12000000, 816000000, 816, 12, 1, 12},
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{ 13000000, 816000000, 816, 13, 1, 12},
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{ 19200000, 816000000, 680, 16, 1, 8},
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{ 26000000, 816000000, 816, 26, 1, 12},
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/* 760 MHz */
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{ 12000000, 760000000, 760, 12, 1, 12},
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{ 13000000, 760000000, 760, 13, 1, 12},
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{ 19200000, 760000000, 950, 24, 1, 8},
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{ 26000000, 760000000, 760, 26, 1, 12},
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/* 750 MHz */
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{ 12000000, 750000000, 750, 12, 1, 12},
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{ 13000000, 750000000, 750, 13, 1, 12},
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{ 19200000, 750000000, 625, 16, 1, 8},
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{ 26000000, 750000000, 750, 26, 1, 12},
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/* 608 MHz */
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{ 12000000, 608000000, 608, 12, 1, 12},
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{ 13000000, 608000000, 608, 13, 1, 12},
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{ 19200000, 608000000, 380, 12, 1, 8},
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{ 26000000, 608000000, 608, 26, 1, 12},
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/* 456 MHz */
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{ 12000000, 456000000, 456, 12, 1, 12},
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{ 13000000, 456000000, 456, 13, 1, 12},
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{ 19200000, 456000000, 380, 16, 1, 8},
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{ 26000000, 456000000, 456, 26, 1, 12},
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/* 312 MHz */
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{ 12000000, 312000000, 312, 12, 1, 12},
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{ 13000000, 312000000, 312, 13, 1, 12},
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{ 19200000, 312000000, 260, 16, 1, 8},
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{ 26000000, 312000000, 312, 26, 1, 12},
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
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{ 12000000, 480000000, 960, 12, 2, 0},
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{ 13000000, 480000000, 960, 13, 2, 0},
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{ 19200000, 480000000, 200, 4, 2, 0},
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{ 26000000, 480000000, 960, 26, 2, 0},
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{ 0, 0, 0, 0, 0, 0 },
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};
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/* PLL parameters */
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static struct tegra_clk_pll_params pll_c_params = {
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.input_min = 2000000,
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.input_max = 31000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 20000000,
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.vco_max = 1400000000,
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.base_reg = CRC_PLLC_BASE,
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.misc_reg = CRC_PLLC_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_p_params = {
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.input_min = 2000000,
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.input_max = 31000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 20000000,
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.vco_max = 1400000000,
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.base_reg = CRC_PLLP_BASE,
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.misc_reg = CRC_PLLP_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_m_params = {
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.input_min = 2000000,
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.input_max = 31000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 20000000,
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.vco_max = 1200000000,
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.base_reg = CRC_PLLM_BASE,
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.misc_reg = CRC_PLLM_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_x_params = {
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.input_min = 2000000,
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.input_max = 31000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 20000000,
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.vco_max = 1200000000,
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.base_reg = CRC_PLLX_BASE,
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.misc_reg = CRC_PLLX_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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};
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static struct tegra_clk_pll_params pll_u_params = {
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.input_min = 2000000,
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.input_max = 40000000,
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.cf_min = 1000000,
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.cf_max = 6000000,
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.vco_min = 48000000,
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.vco_max = 960000000,
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.base_reg = CRC_PLLU_BASE,
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.misc_reg = CRC_PLLU_MISC,
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.lock_bit_idx = CRC_PLL_BASE_LOCK,
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.lock_enable_bit_idx = CRC_PLLDU_MISC_LOCK_ENABLE,
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.lock_delay = 1000,
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};
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static void tegra20_pll_init(void)
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{
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/* PLLC */
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clks[pll_c] = tegra_clk_register_pll("pll_c", "pll_ref", car_base,
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0, 0, &pll_c_params, TEGRA_PLL_HAS_CPCON,
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pll_c_freq_table);
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clks[pll_c_out1] = tegra_clk_register_pll_out("pll_c_out1", "pll_c",
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car_base + CRC_PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP);
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/* PLLP */
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clks[pll_p] = tegra_clk_register_pll("pll_p", "pll_ref", car_base,
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0, 216000000, &pll_p_params, TEGRA_PLL_FIXED |
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TEGRA_PLL_HAS_CPCON, pll_p_freq_table);
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clks[pll_p_out1] = tegra_clk_register_pll_out("pll_p_out1", "pll_p",
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car_base + CRC_PLLP_OUTA, 0,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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clks[pll_p_out2] = tegra_clk_register_pll_out("pll_p_out2", "pll_p",
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car_base + CRC_PLLP_OUTA, 16,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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clks[pll_p_out3] = tegra_clk_register_pll_out("pll_p_out3", "pll_p",
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car_base + CRC_PLLP_OUTB, 0,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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clks[pll_p_out4] = tegra_clk_register_pll_out("pll_p_out4", "pll_p",
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car_base + CRC_PLLP_OUTB, 16,
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TEGRA_DIVIDER_FIXED | TEGRA_DIVIDER_ROUND_UP);
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/* PLLM */
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clks[pll_m] = tegra_clk_register_pll("pll_m", "pll_ref", car_base,
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0, 0, &pll_m_params, TEGRA_PLL_HAS_CPCON,
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pll_m_freq_table);
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clks[pll_m_out1] = tegra_clk_register_pll_out("pll_m_out1", "pll_m",
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car_base + CRC_PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP);
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/* PLLX */
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clks[pll_x] = tegra_clk_register_pll("pll_x", "pll_ref", car_base,
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0, 0, &pll_x_params, TEGRA_PLL_HAS_CPCON,
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pll_x_freq_table);
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/* PLLU */
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clks[pll_u] = tegra_clk_register_pll("pll_u", "pll_ref", car_base,
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0, 0, &pll_u_params, TEGRA_PLLU |
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TEGRA_PLL_HAS_CPCON, pll_u_freq_table);
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}
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static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
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static void tegra20_periph_init(void)
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{
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/* peripheral clocks without a divider */
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clks[uarta] = tegra_clk_register_periph_nodiv("uarta", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTA, uarta, TEGRA_PERIPH_ON_APB);
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clks[uartb] = tegra_clk_register_periph_nodiv("uartb", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTB, uartb, TEGRA_PERIPH_ON_APB);
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clks[uartc] = tegra_clk_register_periph_nodiv("uartc", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTC, uartc, TEGRA_PERIPH_ON_APB);
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clks[uartd] = tegra_clk_register_periph_nodiv("uartd", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTD, uartd, TEGRA_PERIPH_ON_APB);
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clks[uarte] = tegra_clk_register_periph_nodiv("uarte", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_UARTE, uarte, TEGRA_PERIPH_ON_APB);
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/* peripheral clocks with a divider */
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clks[sdmmc1] = tegra_clk_register_periph("sdmmc1", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC1, sdmmc1, 1);
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clks[sdmmc2] = tegra_clk_register_periph("sdmmc2", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC2, sdmmc2, 1);
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clks[sdmmc3] = tegra_clk_register_periph("sdmmc3", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC3, sdmmc3, 1);
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clks[sdmmc4] = tegra_clk_register_periph("sdmmc4", mux_pllpcm_clkm,
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ARRAY_SIZE(mux_pllpcm_clkm), car_base,
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CRC_CLK_SOURCE_SDMMC4, sdmmc4, 1);
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}
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static struct tegra_clk_init_table init_table[] = {
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{pll_p, clk_max, 216000000, 1},
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{pll_p_out1, clk_max, 28800000, 1},
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{pll_p_out2, clk_max, 48000000, 1},
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{pll_p_out3, clk_max, 72000000, 1},
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{pll_p_out4, clk_max, 24000000, 1},
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{pll_c, clk_max, 600000000, 1},
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{pll_c_out1, clk_max, 120000000, 1},
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{uarta, pll_p, 0, 1},
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{uartb, pll_p, 0, 1},
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{uartc, pll_p, 0, 1},
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{uartd, pll_p, 0, 1},
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{uarte, pll_p, 0, 1},
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{sdmmc1, pll_p, 48000000, 0},
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{sdmmc2, pll_p, 48000000, 0},
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{sdmmc3, pll_p, 48000000, 0},
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{sdmmc4, pll_p, 48000000, 0},
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{clk_max, clk_max, 0, 0}, /* sentinel */
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};
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static int tegra20_car_probe(struct device_d *dev)
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{
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car_base = dev_request_mem_region(dev, 0);
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if (!car_base)
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return -EBUSY;
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tegra20_osc_clk_init();
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tegra20_pll_init();
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tegra20_periph_init();
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tegra_init_from_table(init_table, clks, clk_max);
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/* speed up system bus */
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writel(CRC_SCLK_BURST_POLICY_SYS_STATE_RUN <<
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CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT |
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CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1 <<
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CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT,
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car_base + CRC_SCLK_BURST_POLICY);
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clk_data.clks = clks;
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clk_data.clk_num = ARRAY_SIZE(clks);
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of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
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&clk_data);
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return 0;
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}
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static __maybe_unused struct of_device_id tegra20_car_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-car",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d tegra20_car_driver = {
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.probe = tegra20_car_probe,
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.name = "tegra20-car",
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.of_compatible = DRV_OF_COMPAT(tegra20_car_dt_ids),
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};
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static int tegra20_car_init(void)
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{
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return platform_driver_register(&tegra20_car_driver);
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}
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postcore_initcall(tegra20_car_init);
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