5a9ba98f21
This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the functional driver itself, it also adds SoC specific PHY setup required for PCIe. Currently, only Armada 370 is fully supported. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
209 lines
6.4 KiB
C
209 lines
6.4 KiB
C
/*
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* SoC specific PCIe PHY setup for Marvell MVEBU SoCs
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on Marvell BSP code (C) Marvell International Ltd.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <common.h>
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#include <of.h>
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#include <of_address.h>
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#include "pci-mvebu.h"
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static u32 mvebu_pcie_phy_indirect(void __iomem *phybase, u8 lane,
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u8 off, u16 val, bool is_read)
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{
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u32 reg = (lane << 24) | (off << 16) | val;
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if (is_read)
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reg |= BIT(31);
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writel(reg, phybase);
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return (is_read) ? readl(phybase) & 0xffff : 0;
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}
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static inline u32 mvebu_pcie_phy_read(void __iomem *phybase, u8 lane,
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u8 off)
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{
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return mvebu_pcie_phy_indirect(phybase, lane, off, 0, true);
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}
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static inline void mvebu_pcie_phy_write(void __iomem *phybase, u8 lane,
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u8 off, u16 val)
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{
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mvebu_pcie_phy_indirect(phybase, lane, off, val, false);
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}
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/* PCIe registers */
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#define ARMADA_370_XP_PCIE_LINK_CAPS 0x6c
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#define MAX_LINK_WIDTH_MASK MAX_LINK_WIDTH(0x3f)
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#define MAX_LINK_WIDTH(x) ((x) << 4)
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#define MAX_LINK_SPEED_MASK 0xf
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#define MAX_LINK_SPEED_5G0 0x2
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#define MAX_LINK_SPEED_2G5 0x1
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#define ARMADA_370_XP_PHY_OFFSET 0x1b00
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/* System Control registers */
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#define ARMADA_370_XP_SOC_CTRL 0x04
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#define PCIE1_QUADX1_EN BIT(8) /* Armada XP */
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#define PCIE0_QUADX1_EN BIT(7) /* Armada XP */
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#define PCIE0_EN BIT(0)
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#define ARMADA_370_XP_SERDES03_SEL 0x70
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#define ARMADA_370_XP_SERDES47_SEL 0x74
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#define SERDES(x, v) ((v) << ((x) * 0x4))
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#define SERDES_MASK(x) SERDES((x), 0xf)
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int armada_370_phy_setup(struct mvebu_pcie *pcie)
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{
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struct device_node *np = of_find_compatible_node(NULL, NULL,
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"marvell,armada-370-xp-system-controller");
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void __iomem *sysctrl = of_iomap(np, 0);
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void __iomem *phybase = pcie->base + ARMADA_370_XP_PHY_OFFSET;
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u32 reg;
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if (!sysctrl)
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return -ENODEV;
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/* Enable PEX */
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reg = readl(sysctrl + ARMADA_370_XP_SOC_CTRL);
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reg |= PCIE0_EN << pcie->port;
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writel(reg, sysctrl + ARMADA_370_XP_SOC_CTRL);
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/* Set SERDES selector */
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reg = readl(sysctrl + ARMADA_370_XP_SERDES03_SEL);
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reg &= ~SERDES_MASK(pcie->port);
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reg |= SERDES(pcie->port, 0x1);
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writel(reg, sysctrl + ARMADA_370_XP_SERDES03_SEL);
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/* BTS #232 - PCIe clock (undocumented) */
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writel(0x00000077, sysctrl + 0x2f0);
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/* Set x1 Link Capability */
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reg = readl(pcie->base + ARMADA_370_XP_PCIE_LINK_CAPS);
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reg &= ~(MAX_LINK_WIDTH_MASK | MAX_LINK_SPEED_MASK);
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reg |= MAX_LINK_WIDTH(0x1) | MAX_LINK_SPEED_5G0;
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writel(reg, pcie->base + ARMADA_370_XP_PCIE_LINK_CAPS);
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/* PEX pipe configuration */
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc1, 0x0025);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc3, 0x000f);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc8, 0x0005);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xd0, 0x0100);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xd1, 0x3014);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc5, 0x011f);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x80, 0x1000);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x81, 0x0011);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x0f, 0x2a21);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x45, 0x00df);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x4f, 0x6219);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x01, 0xfc60);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x46, 0x0000);
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reg = mvebu_pcie_phy_read(phybase, pcie->lane, 0x48) & ~0x4;
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x48, reg & 0xffff);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x02, 0x0040);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc1, 0x0024);
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mdelay(15);
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return 0;
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}
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/*
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* MV78230: 2 PCIe units Gen2.0, one unit 1x4 or 4x1, one unit 1x1
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* MV78260: 3 PCIe units Gen2.0, two units 1x4 or 4x1, one unit 1x1/1x4
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* MV78460: 4 PCIe units Gen2.0, two units 1x4 or 4x1, two units 1x1/1x4
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*/
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#define ARMADA_XP_COMM_PHY_REFCLK_ALIGN 0xf8
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#define REFCLK_ALIGN(x) (0xf << ((x) * 0x4))
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int armada_xp_phy_setup(struct mvebu_pcie *pcie)
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{
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struct device_node *np = of_find_compatible_node(NULL, NULL,
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"marvell,armada-370-xp-system-controller");
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void __iomem *sysctrl = of_iomap(np, 0);
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void __iomem *phybase = pcie->base + ARMADA_370_XP_PHY_OFFSET;
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u32 serdes_off = (pcie->port < 2) ? ARMADA_370_XP_SERDES03_SEL :
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ARMADA_370_XP_SERDES47_SEL;
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bool single_x4 = (pcie->lane_mask == 0xf);
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u32 reg, mask;
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if (!sysctrl)
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return -ENODEV;
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/* Prepare PEX */
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reg = readl(sysctrl + ARMADA_370_XP_SOC_CTRL);
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reg &= ~(PCIE0_EN << pcie->port);
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writel(reg, sysctrl + ARMADA_370_XP_SOC_CTRL);
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if (pcie->port < 2) {
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mask = PCIE0_QUADX1_EN << pcie->port;
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if (single_x4)
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reg &= ~mask;
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else
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reg |= mask;
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}
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reg |= PCIE0_EN << pcie->port;
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writel(reg, sysctrl + ARMADA_370_XP_SOC_CTRL);
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/* Set SERDES selector */
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reg = readl(sysctrl + serdes_off);
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for (mask = pcie->lane_mask; mask;) {
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u32 l = ffs(mask)-1;
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u32 off = 4 * (pcie->port % 2);
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reg &= ~SERDES_MASK(off + l);
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reg |= SERDES(off + l, 0x1);
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mask &= ~BIT(l);
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}
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reg &= ~SERDES_MASK(pcie->port % 2);
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reg |= SERDES(pcie->port % 2, 0x1);
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writel(reg, sysctrl + serdes_off);
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/* Reference Clock Alignment for 1x4 */
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reg = readl(sysctrl + ARMADA_XP_COMM_PHY_REFCLK_ALIGN);
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if (single_x4)
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reg |= REFCLK_ALIGN(pcie->port);
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else
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reg &= ~REFCLK_ALIGN(pcie->port);
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writel(reg, sysctrl + ARMADA_XP_COMM_PHY_REFCLK_ALIGN);
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/* Set x1/x4 Link Capability */
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reg = readl(pcie->base + ARMADA_370_XP_PCIE_LINK_CAPS);
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reg &= ~(MAX_LINK_WIDTH_MASK | MAX_LINK_SPEED_MASK);
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if (single_x4)
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reg |= MAX_LINK_WIDTH(0x4);
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else
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reg |= MAX_LINK_WIDTH(0x1);
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reg |= MAX_LINK_SPEED_5G0;
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writel(reg, pcie->base + ARMADA_370_XP_PCIE_LINK_CAPS);
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/* PEX pipe configuration */
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc1, 0x0025);
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if (single_x4) {
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc2, 0x0200);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc3, 0x0001);
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} else {
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc2, 0x0000);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc3, 0x000f);
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}
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc8, 0x0005);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x01, 0xfc60);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x46, 0x0000);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x02, 0x0040);
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mvebu_pcie_phy_write(phybase, pcie->lane, 0xc1, 0x0024);
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if (single_x4)
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x48, 0x1080);
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else
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mvebu_pcie_phy_write(phybase, pcie->lane, 0x48, 0x9080);
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mdelay(15);
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return 0;
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}
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