41 lines
989 B
ArmAsm
41 lines
989 B
ArmAsm
/*
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* reset AT91SAM9G45 as per errata
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*
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* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
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*
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* unless the SDRAM is cleanly shutdown before we hit the
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* reset register it can be left driving the data bus and
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* killing the chance of a subsequent boot from NAND
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*
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* GPLv2 Only
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*/
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#include <linux/linkage.h>
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#include <mach/hardware.h>
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#include <mach/at91sam9_ddrsdr.h>
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#include <mach/at91_rstc.h>
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.arm
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.globl reset_cpu
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reset_cpu: ldr r0, .at91_va_base_sdramc @ preload constants
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ldr r1, .at91_va_base_rstc_cr
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mov r2, #1
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mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
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ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
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.balign 32 @ align to cache line
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str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
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str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
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str r4, [r1] @ reset processor
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b .
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.at91_va_base_sdramc:
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.word AT91_BASE_SYS + AT91_DDRSDRC0
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.at91_va_base_rstc_cr:
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.word AT91_BASE_SYS + AT91_RSTC_CR
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