184 lines
6.3 KiB
C
184 lines
6.3 KiB
C
/*
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* Chip-specific header file for the AT91SAM9N12 SoC
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*
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* Copyright (C) 2011 Atmel Corporation
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*
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* Common definitions.
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* Based on AT91SAM9N12 preliminary datasheet
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __MACH_AT91SAM9N12_H_
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#define __MACH_AT91SAM9N12_H_
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define AT91_ID_SYS 1 /* System Controller Interrupt */
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#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
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#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
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/* Reserved 4 */
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#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
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#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
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#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
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#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
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#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
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#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
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/* Reserved 11 */
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#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface 0 */
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#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
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#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
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#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
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#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
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#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
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#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
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#define AT91SAM9N12_ID_DMA 20 /* DMA Controller 0 */
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/* Reserved 21 */
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#define AT91SAM9N12_ID_UHPFS 22 /* USB Host Full Speed */
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#define AT91SAM9N12_ID_UDPFS 23 /* USB Device Full Speed */
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/* Reserved 24 */
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#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
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/* Reserved 26 */
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/* Reserved 27 */
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#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
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/* Reserved 29 */
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#define AT91SAM9N12_ID_TRNG 30 /* True Random Number Generator */
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#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91SAM9N12_BASE_SPI0 0xf0000000
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#define AT91SAM9N12_BASE_SPI1 0xf0004000
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#define AT91SAM9N12_BASE_MCI 0xf0008000
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#define AT91SAM9N12_BASE_SSC 0xf0010000
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#define AT91SAM9N12_BASE_TCB0 0xf8008000
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#define AT91SAM9N12_BASE_TC0 0xf8008000
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#define AT91SAM9N12_BASE_TC1 0xf8008040
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#define AT91SAM9N12_BASE_TC2 0xf8008080
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#define AT91SAM9N12_BASE_TCB1 0xf800c000
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#define AT91SAM9N12_BASE_TC3 0xf800c000
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#define AT91SAM9N12_BASE_TC4 0xf800c040
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#define AT91SAM9N12_BASE_TC5 0xf800c080
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#define AT91SAM9N12_BASE_TWI0 0xf8010000
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#define AT91SAM9N12_BASE_TWI1 0xf8014000
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#define AT91SAM9N12_BASE_USART0 0xf801c000
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#define AT91SAM9N12_BASE_USART1 0xf8020000
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#define AT91SAM9N12_BASE_USART2 0xf8024000
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#define AT91SAM9N12_BASE_USART3 0xf8028000
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#define AT91SAM9N12_BASE_PWMC 0xf8034000
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#define AT91SAM9N12_BASE_LCDC 0xf8038000
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#define AT91SAM9N12_BASE_UDPFS 0xf803c000
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#define AT91SAM9N12_BASE_UART0 0xf8040000
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#define AT91SAM9N12_BASE_UART1 0xf8044000
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#define AT91SAM9N12_BASE_TRNG 0xf8048000
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#define AT91SAM9N12_BASE_ADC 0xf804c000
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#define AT91_BASE_SYS 0xffffc000
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/*
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* System Peripherals
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*/
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#define AT91SAM9N12_BASE_FUSE 0xffffdc00
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#define AT91SAM9N12_BASE_MATRIX 0xffffde00
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#define AT91SAM9N12_BASE_PMECC 0xffffe000
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#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600
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#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800
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#define AT91SAM9N12_BASE_SMC 0xffffea00
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#define AT91SAM9N12_BASE_DMA 0xffffec00
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#define AT91SAM9N12_BASE_AIC 0xfffff000
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#define AT91SAM9N12_BASE_DBGU 0xfffff200
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#define AT91SAM9N12_BASE_PIOA 0xfffff400
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#define AT91SAM9N12_BASE_PIOB 0xfffff600
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#define AT91SAM9N12_BASE_PIOC 0xfffff800
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#define AT91SAM9N12_BASE_PIOD 0xfffffa00
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#define AT91SAM9N12_BASE_PMC 0xfffffc00
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#define AT91SAM9N12_BASE_RSTC 0xfffffe00
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#define AT91SAM9N12_BASE_SHDWC 0xfffffe10
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#define AT91SAM9N12_BASE_PIT 0xfffffe30
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#define AT91SAM9N12_BASE_WDT 0xfffffe40
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#define AT91SAM9N12_BASE_GPBR 0xfffffe60
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#define AT91SAM9N12_BASE_RTC 0xfffffeb0
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
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#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
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#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
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#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
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#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
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#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT
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#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
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#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
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#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
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#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
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#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD
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#define AT91_USART0 AT91SAM9X5_BASE_US0
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#define AT91_USART1 AT91SAM9X5_BASE_US1
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#define AT91_USART2 AT91SAM9X5_BASE_US2
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#define AT91_USART3 AT91SAM9X5_BASE_US3
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#define AT91_NB_USART 5
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/*
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* Internal Memory.
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*/
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#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
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#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
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#define AT91SAM9N12_ROM_SIZE SZ_1M /* Internal ROM size (1Mb) */
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#define AT91SAM9N12_SMD_BASE 0x00400000 /* SMD Controller */
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#define AT91SAM9N12_OHCI_BASE 0x00500000 /* USB Host controller (OHCI) */
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#define CONFIG_DRAM_BASE AT91_CHIPSELECT_1
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#define CONSISTENT_DMA_SIZE (14 * SZ_1M)
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/*
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* DMA0 peripheral identifiers
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* for hardware handshaking interface
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*/
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#define AT_DMA_ID_MCI 0
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#define AT_DMA_ID_SPI0_TX 1
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#define AT_DMA_ID_SPI0_RX 2
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#define AT_DMA_ID_SPI1_TX 3
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#define AT_DMA_ID_SPI1_RX 4
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#define AT_DMA_ID_USART0_TX 5
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#define AT_DMA_ID_USART0_RX 6
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#define AT_DMA_ID_USART1_TX 7
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#define AT_DMA_ID_USART1_RX 8
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#define AT_DMA_ID_USART2_TX 9
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#define AT_DMA_ID_USART2_RX 10
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#define AT_DMA_ID_USART3_TX 11
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#define AT_DMA_ID_USART3_RX 12
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#define AT_DMA_ID_TWI0_TX 13
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#define AT_DMA_ID_TWI0_RX 14
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#define AT_DMA_ID_TWI1_TX 15
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#define AT_DMA_ID_TWI1_RX 16
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#define AT_DMA_ID_UART0_TX 17
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#define AT_DMA_ID_UART0_RX 18
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#define AT_DMA_ID_UART1_TX 19
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#define AT_DMA_ID_UART1_RX 20
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#define AT_DMA_ID_SSC_TX 21
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#define AT_DMA_ID_SSC_RX 22
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#define AT_DMA_ID_ADC_RX 23
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#define AT_DMA_ID_DBGU_TX 24
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#define AT_DMA_ID_DBGU_RX 25
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#define AT_DMA_ID_AES_TX 26
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#define AT_DMA_ID_AES_RX 27
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#define AT_DMA_ID_SHA_RX 28
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#endif
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