206 lines
4.8 KiB
C
206 lines
4.8 KiB
C
/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <clock.h>
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#include <errno.h>
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#include <notifier.h>
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#include <mach/imx-regs.h>
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#include <mach/clock.h>
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#include <io.h>
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/* Part 1: Registers */
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# define GPT_TCTL 0x00
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# define GPT_TPRER 0x04
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/* Part 2: Bitfields */
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#define TCTL_SWR (1 << 15) /* Software reset */
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#define IMX1_TCTL_FRR (1 << 8) /* Freerun / restart */
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#define IMX31_TCTL_FRR (1 << 9) /* Freerun / restart */
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#define IMX1_TCTL_CLKSOURCE_IPG (1 << 1) /* Clock source bit position */
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#define IMX31_TCTL_CLKSOURCE_IPG (1 << 6) /* Clock source bit position */
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#define TCTL_TEN (1 << 0) /* Timer enable */
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struct imx_gpt_regs {
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unsigned int tcn;
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uint32_t tctl_val;
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};
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static struct imx_gpt_regs regs_imx1 = {
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.tcn = 0x10,
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.tctl_val = IMX1_TCTL_FRR | IMX1_TCTL_CLKSOURCE_IPG | TCTL_TEN,
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};
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static struct imx_gpt_regs regs_imx31 = {
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.tcn = 0x24,
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.tctl_val = IMX31_TCTL_FRR | IMX31_TCTL_CLKSOURCE_IPG | TCTL_TEN,
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};
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static struct imx_gpt_regs *regs;
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static void __iomem *timer_base;
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static uint64_t imx_clocksource_read(void)
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{
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return readl(timer_base + regs->tcn);
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}
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static struct clocksource cs = {
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.read = imx_clocksource_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 10,
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};
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static int imx_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data)
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{
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cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift);
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return 0;
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}
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static struct notifier_block imx_clock_notifier = {
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.notifier_call = imx_clocksource_clock_change,
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};
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static int imx_gpt_probe(struct device_d *dev)
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{
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int i;
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int ret;
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/* one timer is enough */
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if (timer_base)
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return -EBUSY;
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ret = dev_get_drvdata(dev, (unsigned long *)®s);
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if (ret)
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return ret;
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timer_base = dev_request_mem_region(dev, 0);
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/* setup GP Timer 1 */
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writel(TCTL_SWR, timer_base + GPT_TCTL);
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#ifdef CONFIG_ARCH_IMX21
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PCCR1 |= PCCR1_GPT1_EN;
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#endif
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#ifdef CONFIG_ARCH_IMX27
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PCCR0 |= PCCR0_GPT1_EN;
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PCCR1 |= PCCR1_PERCLK1_EN;
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#endif
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#ifdef CONFIG_ARCH_IMX25
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writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19),
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IMX_CCM_BASE + CCM_CGCR1);
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#endif
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for (i = 0; i < 100; i++)
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writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
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writel(0, timer_base + GPT_TPRER);
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writel(regs->tctl_val, timer_base + GPT_TCTL);
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cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift);
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init_clock(&cs);
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clock_register_client(&imx_clock_notifier);
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return 0;
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}
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static __maybe_unused struct of_device_id imx_gpt_dt_ids[] = {
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{
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.compatible = "fsl,imx1-gpt",
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.data = (unsigned long)®s_imx1,
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}, {
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.compatible = "fsl,imx31-gpt",
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.data = (unsigned long)®s_imx31,
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}, {
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/* sentinel */
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}
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};
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static struct platform_device_id imx_gpt_ids[] = {
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{
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.name = "imx1-gpt",
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.driver_data = (unsigned long)®s_imx1,
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}, {
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.name = "imx31-gpt",
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.driver_data = (unsigned long)®s_imx31,
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}, {
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/* sentinel */
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},
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};
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static struct driver_d imx_gpt_driver = {
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.name = "imx-gpt",
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.probe = imx_gpt_probe,
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.of_compatible = DRV_OF_COMPAT(imx_gpt_dt_ids),
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.id_table = imx_gpt_ids,
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};
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static int imx_gpt_init(void)
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{
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return platform_driver_register(&imx_gpt_driver);
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}
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coredevice_initcall(imx_gpt_init);
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/*
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* Watchdog Registers
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*/
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#ifdef CONFIG_ARCH_IMX1
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#define WDOG_WCR 0x00 /* Watchdog Control Register */
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#define WDOG_WSR 0x04 /* Watchdog Service Register */
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#define WDOG_WSTR 0x08 /* Watchdog Status Register */
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#define WDOG_WCR_WDE (1 << 0)
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#else
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#define WDOG_WCR 0x00 /* Watchdog Control Register */
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#define WDOG_WSR 0x02 /* Watchdog Service Register */
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#define WDOG_WSTR 0x04 /* Watchdog Status Register */
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#define WDOG_WCR_WDE (1 << 2)
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#endif
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/*
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* Reset the cpu by setting up the watchdog timer and let it time out
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*/
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void __noreturn reset_cpu (unsigned long addr)
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{
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void __iomem *wdt = IOMEM(IMX_WDT_BASE);
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/* Disable watchdog and set Time-Out field to 0 */
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writew(0x0, wdt + WDOG_WCR);
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/* Write Service Sequence */
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writew(0x5555, wdt + WDOG_WSR);
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writew(0xaaaa, wdt + WDOG_WSR);
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/* Enable watchdog */
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writew(WDOG_WCR_WDE, wdt + WDOG_WCR);
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while (1);
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/*NOTREACHED*/
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}
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EXPORT_SYMBOL(reset_cpu);
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