152 lines
3.2 KiB
C
152 lines
3.2 KiB
C
/*
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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/* ------------------------------------------------------------------------- */
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int checkcpu (void)
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{
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uint pir = get_pir();
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uint pvr = get_pvr();
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printf("Motorola PowerPC ProcessorID=%08x Rev. ",pir);
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switch(pvr) {
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default:
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printf("PVR=%08x", pvr);
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break;
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}
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printf("\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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/*
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* Initiate hard reset in debug control register DBCR0
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* Make sure MSR[DE] = 1
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*/
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__asm__ __volatile__("lis 3, 0x7000" ::: "r3");
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mtspr(DBCR0,3);
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk (void)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return ((sys_info.freqSystemBus + 3L) / 4L);
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_85xx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void
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reset_85xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit by writing 1
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*/
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unsigned long val;
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val = mfspr(tsr);
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val |= 0x40000000;
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mtspr(tsr, val);
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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__inline__ void dcbz(const void* addr)
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{
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__asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr));
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}
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__inline__ void dcbf(const void* addr)
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{
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__asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr));
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}
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void dma_init(void) {
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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dma->satr0 = 0x02c40000;
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dma->datr0 = 0x02c40000;
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asm("sync; isync; msync");
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return;
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}
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uint dma_check(void) {
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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volatile uint status = dma->sr0;
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/* While the channel is busy, spin */
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while((status & 4) == 4) {
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status = dma->sr0;
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}
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if (status != 0) {
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printf ("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int dma_xfer(void *dest, uint count, void *src) {
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_dma_t *dma = &immap->im_dma;
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dma->dar0 = (uint) dest;
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dma->sar0 = (uint) src;
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dma->bcr0 = count;
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dma->mr0 = 0xf000004;
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asm("sync;isync;msync");
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dma->mr0 = 0xf000005;
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asm("sync;isync;msync");
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return dma_check();
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}
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#endif
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