207 lines
6.2 KiB
C
207 lines
6.2 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <asm/processor.h>
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#define PITC_SHIFT 16
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#define PITR_SHIFT 16
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/* pitc values to time for 58/8192 seconds (about 70.8 milliseconds) */
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#define SPEED_PIT_COUNTS 58
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#define SPEED_PITC ((SPEED_PIT_COUNTS - 1) << PITC_SHIFT)
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#define SPEED_PITC_INIT ((SPEED_PIT_COUNTS + 1) << PITC_SHIFT)
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/* Access functions for the Machine State Register */
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static __inline__ unsigned long get_msr(void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr;
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}
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static __inline__ void set_msr(unsigned long msr)
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{
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asm volatile("mtmsr %0" : : "r" (msr));
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Measure CPU clock speed (core clock GCLK1, GCLK2),
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* also determine bus clock speed (checking bus divider factor)
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*
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* (Approx. GCLK frequency in Hz)
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*
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* Initializes timer 2 and PIT, but disables them before return.
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* [Use timer 2, because MPC823 CPUs mask 0.x do not have timers 3 and 4]
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*
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* When measuring the CPU clock against the PIT, we count cpu clocks
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* for 58/8192 seconds with a prescale divide by 177 for the cpu clock.
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* These strange values for the timing interval and prescaling are used
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* because the formula for the CPU clock is:
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*
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* CPU clock = count * (177 * (8192 / 58))
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*
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* = count * 24999.7241
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*
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* which is very close to
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*
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* = count * 25000
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*
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* Since the count gives the CPU clock divided by 25000, we can get
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* the CPU clock rounded to the nearest 0.1 MHz by
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*
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* CPU clock = ((count + 2) / 4) * 100000;
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*
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* The rounding is important since the measurement is sometimes going
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* to be high or low by 0.025 MHz, depending on exactly how the clocks
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* and counters interact. By rounding we get the exact answer for any
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* CPU clock that is an even multiple of 0.1 MHz.
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*/
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unsigned long measure_gclk(void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile cpmtimer8xx_t *timerp = &immr->im_cpmtimer;
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ulong timer2_val;
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ulong msr_val;
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#ifdef CONFIG_MPC866_et_al
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/* dont use OSCM, only use EXTCLK/512 */
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immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
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#else
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immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
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#endif
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/* Reset + Stop Timer 2, no cascading
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*/
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timerp->cpmt_tgcr &= ~(TGCR_CAS2 | TGCR_RST2);
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/* Keep stopped, halt in debug mode
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*/
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timerp->cpmt_tgcr |= (TGCR_FRZ2 | TGCR_STP2);
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/* Timer 2 setup:
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* Output ref. interrupt disable, int. clock
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* Prescale by 177. Note that prescaler divides by value + 1
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* so we must subtract 1 here.
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*/
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timerp->cpmt_tmr2 = ((177 - 1) << TMR_PS_SHIFT) | TMR_ICLK_IN_GEN;
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timerp->cpmt_tcn2 = 0; /* reset state */
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timerp->cpmt_tgcr |= TGCR_RST2; /* enable timer 2 */
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/*
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* PIT setup:
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*
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* We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
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* so the count value would be SPEED_PITC_COUNTS - 1.
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* But there would be an uncertainty in the start time of 1/4
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* count since when we enable the PIT the count is not
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* synchronized to the 32768 Hz oscillator. The trick here is
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* to start the count higher and wait until the PIT count
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* changes to the required value before starting timer 2.
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*
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* One count high should be enough, but occasionally the start
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* is off by 1 or 2 counts of 32768 Hz. With the start value
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* set two counts high it seems very reliable.
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*/
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immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
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immr->im_sit.sit_pitc = SPEED_PITC_INIT;
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immr->im_sitk.sitk_piscrk = KAPWR_KEY;
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immr->im_sit.sit_piscr = CFG_PISCR;
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/*
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* Start measurement - disable interrupts, just in case
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*/
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msr_val = get_msr ();
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set_msr (msr_val & ~MSR_EE);
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immr->im_sit.sit_piscr |= PISCR_PTE;
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/* spin until get exact count when we want to start */
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while (immr->im_sit.sit_pitr > SPEED_PITC);
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timerp->cpmt_tgcr &= ~TGCR_STP2; /* Start Timer 2 */
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while ((immr->im_sit.sit_piscr & PISCR_PS) == 0);
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timerp->cpmt_tgcr |= TGCR_STP2; /* Stop Timer 2 */
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/* re-enable external interrupts if they were on */
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set_msr (msr_val);
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/* Disable timer and PIT
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*/
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timer2_val = timerp->cpmt_tcn2; /* save before reset timer */
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timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
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immr->im_sit.sit_piscr &= ~PISCR_PTE;
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#ifdef CONFIG_MPC866_et_al
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/* not using OSCM, using XIN, so scale appropriately */
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return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
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#else
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return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
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#endif
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}
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/*
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* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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* or (if it is not defined) measure_gclk() (which uses the ref clock)
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* from above.
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*/
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int get_clocks (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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#ifndef CONFIG_8xx_GCLK_FREQ
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gd->cpu_clk = measure_gclk();
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#else /* CONFIG_8xx_GCLK_FREQ */
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/*
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* If for some reason measuring the gclk frequency won't
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* work, we return the hardwired value.
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* (For example, the cogent CMA286-60 CPU module has no
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* separate oscillator for PITRTCLK)
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*/
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gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
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#endif /* CONFIG_8xx_GCLK_FREQ */
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
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/* No Bus Divider active */
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gd->bus_clk = gd->cpu_clk;
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} else {
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/* The MPC8xx has only one BDF: half clock speed */
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gd->bus_clk = gd->cpu_clk / 2;
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}
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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