91 lines
3.0 KiB
C
91 lines
3.0 KiB
C
/*
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* Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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*/
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#ifndef _ASM_GT64120_H
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#define _ASM_GT64120_H
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#define MSK(n) ((1 << (n)) - 1)
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#define GT_DEF_BASE 0x14000000
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/*
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* Register offset addresses
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*/
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/* CPU Address Decode. */
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#define GT_PCI0IOLD_OFS 0x048
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#define GT_PCI0IOHD_OFS 0x050
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#define GT_PCI0M0LD_OFS 0x058
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#define GT_PCI0M0HD_OFS 0x060
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#define GT_ISD_OFS 0x068
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#define GT_PCI0M1LD_OFS 0x080
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#define GT_PCI0M1HD_OFS 0x088
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#define GT_PCI0IOREMAP_OFS 0x0f0
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#define GT_PCI0M0REMAP_OFS 0x0f8
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#define GT_PCI0M1REMAP_OFS 0x100
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/* Interrupts. */
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#define GT_INTRCAUSE_OFS 0xc18
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/* PCI Internal. */
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#define GT_PCI0_CMD_OFS 0xc00
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#define GT_PCI0_CFGADDR_OFS 0xcf8
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#define GT_PCI0_CFGDATA_OFS 0xcfc
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#define GT_PCI_DCRM_SHF 21
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#define GT_PCI_LD_SHF 0
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#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
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#define GT_PCI_HD_SHF 0
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#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
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#define GT_PCI_REMAP_SHF 0
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#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
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#define GT_INTRCAUSE_MASABORT0_SHF 18
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#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
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#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
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#define GT_INTRCAUSE_TARABORT0_SHF 19
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#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
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#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
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#define GT_PCI0_CFGADDR_REGNUM_SHF 2
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#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
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#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
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#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
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#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
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#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
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#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
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#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
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#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
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#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
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#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
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/*
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* Because of an error/peculiarity in the Galileo chip, we need to swap the
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* bytes when running bigendian. We also provide non-swapping versions.
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*/
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#define __GT_READ(ofs) \
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(*(volatile u32 *)(GT64120_BASE+(ofs)))
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#define __GT_WRITE(ofs, data) \
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do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
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#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
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#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
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#endif /* _ASM_GT64120_H */
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