For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006-2007 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (c) 2014 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <io.h>
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#include <linux/err.h>
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#define readl_relaxed readl
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#define writel_relaxed writel
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struct davinci_gpio_regs {
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u32 dir;
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u32 out_data;
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u32 set_data;
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u32 clr_data;
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u32 in_data;
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u32 set_rising;
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u32 clr_rising;
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u32 set_falling;
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u32 clr_falling;
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u32 intstat;
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};
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struct davinci_gpio_controller {
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struct gpio_chip chip;
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/* Serialize access to GPIO registers */
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void __iomem *regs;
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void __iomem *set_data;
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void __iomem *clr_data;
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void __iomem *in_data;
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};
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#define chip2controller(chip) \
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container_of(chip, struct davinci_gpio_controller, chip)
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static struct davinci_gpio_regs __iomem *gpio2regs(void __iomem *gpio_base,
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unsigned gpio)
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{
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void __iomem *ptr;
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if (gpio < 32 * 1)
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ptr = gpio_base + 0x10;
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else if (gpio < 32 * 2)
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ptr = gpio_base + 0x38;
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else if (gpio < 32 * 3)
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ptr = gpio_base + 0x60;
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else if (gpio < 32 * 4)
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ptr = gpio_base + 0x88;
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else if (gpio < 32 * 5)
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ptr = gpio_base + 0xb0;
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else
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ptr = NULL;
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return ptr;
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}
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static int davinci_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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return ((readl_relaxed(&g->dir)) & (1 << offset)) ?
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GPIOF_DIR_IN : GPIOF_DIR_OUT;
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}
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static inline int __davinci_direction(struct gpio_chip *chip,
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unsigned offset, bool out, int value)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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u32 temp;
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u32 mask = 1 << offset;
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temp = readl_relaxed(&g->dir);
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if (out) {
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temp &= ~mask;
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writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
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} else {
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temp |= mask;
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}
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writel_relaxed(temp, &g->dir);
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return 0;
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}
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static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
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{
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return __davinci_direction(chip, offset, false, 0);
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}
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static int
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davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
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{
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return __davinci_direction(chip, offset, true, value);
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}
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/*
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* Read the pin's value (works even if it's set up as output);
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* returns zero/nonzero.
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*
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* Note that changes are synched to the GPIO clock, so reading values back
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* right after you've set them may give old values.
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*/
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static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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return (1 << offset) & readl_relaxed(&g->in_data);
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}
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/*
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* Assuming the pin is muxed as a gpio output, set its output value.
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*/
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static void
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davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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writel_relaxed((1 << offset), value ? &g->set_data : &g->clr_data);
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}
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static struct gpio_ops davinci_gpio_ops = {
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.direction_input = davinci_direction_in,
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.direction_output = davinci_direction_out,
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.get_direction = davinci_get_direction,
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.get = davinci_gpio_get,
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.set = davinci_gpio_set,
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};
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static int davinci_gpio_probe(struct device_d *dev)
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{
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void __iomem *gpio_base;
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int ret;
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u32 val;
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int i, base;
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unsigned ngpio;
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struct davinci_gpio_controller *chips;
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ret = of_property_read_u32(dev->device_node, "ti,ngpio", &val);
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if (ret) {
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dev_err(dev, "could not read 'ti,ngpio' property\n");
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return -EINVAL;
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}
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ngpio = val;
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if (WARN_ON(ARCH_NR_GPIOS < ngpio))
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ngpio = ARCH_NR_GPIOS;
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chips = xzalloc((ngpio / 32 + 1) * sizeof(*chips));
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gpio_base = dev_request_mem_region(dev, 0);
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if (IS_ERR(gpio_base)) {
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dev_err(dev, "could not get memory region\n");
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return PTR_ERR(gpio_base);
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}
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for (i = 0, base = 0; base < ngpio; i++, base += 32) {
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struct davinci_gpio_regs __iomem *regs;
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struct gpio_chip *gc;
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gc = &chips[i].chip;
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gc->ops = &davinci_gpio_ops;
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gc->dev = dev;
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gc->base = base;
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gc->ngpio = ngpio - base;
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if (gc->ngpio > 32)
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gc->ngpio = 32;
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regs = gpio2regs(gpio_base, base);
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chips[i].regs = regs;
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chips[i].set_data = ®s->set_data;
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chips[i].clr_data = ®s->clr_data;
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chips[i].in_data = ®s->in_data;
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gpiochip_add(gc);
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}
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return 0;
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}
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static struct of_device_id davinci_gpio_ids[] = {
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{ .compatible = "ti,dm6441-gpio", },
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{ /* sentinel */ },
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};
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static struct driver_d davinci_gpio_driver = {
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.name = "davinci_gpio",
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.probe = davinci_gpio_probe,
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.of_compatible = DRV_OF_COMPAT(davinci_gpio_ids),
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};
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static int davinci_gpio_drv_reg(void)
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{
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return platform_driver_register(&davinci_gpio_driver);
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}
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coredevice_initcall(davinci_gpio_drv_reg);
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