For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
207 lines
5.1 KiB
C
207 lines
5.1 KiB
C
/* *
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* Copyright (C) 2010 Erik Gilling <konkers@google.com>, Google, Inc
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <gpio.h>
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#include <init.h>
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#include <io.h>
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#include <linux/err.h>
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#define GPIO_BANK(x) ((x) >> 5)
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#define GPIO_PORT(x) (((x) >> 3) & 0x3)
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#define GPIO_BIT(x) ((x) & 0x7)
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#define GPIO_REG(x) (GPIO_BANK(x) * config->bank_stride + \
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GPIO_PORT(x) * 4)
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#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
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#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
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#define GPIO_OUT(x) (GPIO_REG(x) + 0x20)
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#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
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#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
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#define GPIO_MSK_CNF(x) (GPIO_REG(x) + config->upper_offset + 0x00)
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#define GPIO_MSK_OE(x) (GPIO_REG(x) + config->upper_offset + 0x10)
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#define GPIO_MSK_OUT(x) (GPIO_REG(x) + config->upper_offset + 0X20)
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struct tegra_gpio_soc_config {
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u32 bank_stride;
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u32 upper_offset;
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u32 bank_count;
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};
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static void __iomem *gpio_base;
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static struct tegra_gpio_soc_config *config;
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static inline void tegra_gpio_writel(u32 val, u32 reg)
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{
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writel(val, gpio_base + reg);
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}
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static inline u32 tegra_gpio_readl(u32 reg)
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{
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return readl(gpio_base + reg);
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}
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static int tegra_gpio_compose(int bank, int port, int bit)
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{
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return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
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}
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static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
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{
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u32 val;
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val = 0x100 << GPIO_BIT(gpio);
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if (value)
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val |= 1 << GPIO_BIT(gpio);
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tegra_gpio_writel(val, reg);
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}
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static void tegra_gpio_enable(int gpio)
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{
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tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
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}
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static void tegra_gpio_disable(int gpio)
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{
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tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
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}
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static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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return 0;
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}
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static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
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{
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tegra_gpio_disable(offset);
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}
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static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
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}
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static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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/* If gpio is in output mode then read from the out value */
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if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1) {
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return (tegra_gpio_readl(GPIO_OUT(offset)) >>
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GPIO_BIT(offset)) & 0x1;
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}
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return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
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}
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static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
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tegra_gpio_enable(offset);
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return 0;
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}
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static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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tegra_gpio_set(chip, offset, value);
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tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
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tegra_gpio_enable(offset);
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return 0;
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}
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static struct gpio_ops tegra_gpio_ops = {
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.request = tegra_gpio_request,
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.free = tegra_gpio_free,
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.direction_input = tegra_gpio_direction_input,
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.direction_output = tegra_gpio_direction_output,
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.get = tegra_gpio_get,
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.set = tegra_gpio_set,
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};
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static struct gpio_chip tegra_gpio_chip = {
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.ops = &tegra_gpio_ops,
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.base = 0,
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};
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static int tegra_gpio_probe(struct device_d *dev)
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{
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int i, j, ret;
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ret = dev_get_drvdata(dev, (unsigned long *)&config);
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if (ret) {
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dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
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return ret;
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}
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gpio_base = dev_request_mem_region(dev, 0);
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if (IS_ERR(gpio_base)) {
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dev_err(dev, "could not get memory region\n");
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return PTR_ERR(gpio_base);
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}
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for (i = 0; i < config->bank_count; i++) {
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for (j = 0; j < 4; j++) {
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int gpio = tegra_gpio_compose(i, j, 0);
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tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
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}
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}
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tegra_gpio_chip.ngpio = config->bank_count * 32;
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tegra_gpio_chip.dev = dev;
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gpiochip_add(&tegra_gpio_chip);
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return 0;
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}
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static struct tegra_gpio_soc_config tegra20_gpio_config = {
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.bank_stride = 0x80,
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.upper_offset = 0x800,
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.bank_count = 7,
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};
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static struct tegra_gpio_soc_config tegra30_gpio_config = {
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.bank_stride = 0x100,
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.upper_offset = 0x80,
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.bank_count = 8,
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};
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static __maybe_unused struct of_device_id tegra_gpio_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-gpio",
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.data = (unsigned long)&tegra20_gpio_config
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}, {
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.compatible = "nvidia,tegra30-gpio",
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.data = (unsigned long)&tegra30_gpio_config
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}, {
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/* sentinel */
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},
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};
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static struct driver_d tegra_gpio_driver = {
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.name = "tegra-gpio",
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.of_compatible = DRV_OF_COMPAT(tegra_gpio_dt_ids),
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.probe = tegra_gpio_probe,
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};
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static int __init tegra_gpio_init(void)
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{
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return platform_driver_register(&tegra_gpio_driver);
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}
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coredevice_initcall(tegra_gpio_init);
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