For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
619 lines
16 KiB
C
619 lines
16 KiB
C
/*
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* Copyright 2007,2010 Freescale Semiconductor, Inc
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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* (C) Copyright 2003
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <of.h>
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#include <malloc.h>
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#include <mci.h>
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#include <clock.h>
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#include <io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <asm/mmu.h>
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#include <mach/generic.h>
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#include <mach/esdhc.h>
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#include <gpio.h>
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#include "sdhci.h"
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#include "imx-esdhc.h"
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#define IMX_SDHCI_WML 0x44
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#define IMX_SDHCI_MIXCTRL 0x48
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struct fsl_esdhc_host {
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struct mci_host mci;
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void __iomem *regs;
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struct device_d *dev;
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struct clk *clk;
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};
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#define to_fsl_esdhc(mci) container_of(mci, struct fsl_esdhc_host, mci)
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#define SDHCI_CMD_ABORTCMD (0xC0 << 16)
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/* Return the XFERTYP flags for a given command and data packet */
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static u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data)
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{
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u32 xfertyp = 0;
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if (data) {
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xfertyp |= COMMAND_DPSEL;
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#ifndef CONFIG_MCI_IMX_ESDHC_PIO
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xfertyp |= TRANSFER_MODE_DMAEN;
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#endif
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if (data->blocks > 1) {
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xfertyp |= TRANSFER_MODE_MSBSEL;
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xfertyp |= TRANSFER_MODE_BCEN;
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}
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if (data->flags & MMC_DATA_READ)
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xfertyp |= TRANSFER_MODE_DTDSEL;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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xfertyp |= COMMAND_CCCEN;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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xfertyp |= COMMAND_CICEN;
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if (cmd->resp_type & MMC_RSP_136)
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xfertyp |= COMMAND_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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xfertyp |= COMMAND_RSPTYP_48_BUSY;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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xfertyp |= COMMAND_RSPTYP_48;
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if ((cpu_is_mx51() || cpu_is_mx53()) &&
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cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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xfertyp |= SDHCI_CMD_ABORTCMD;
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return COMMAND_CMD(cmd->cmdidx) | xfertyp;
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}
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#ifdef CONFIG_MCI_IMX_ESDHC_PIO
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/*
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* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
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*/
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static void
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esdhc_pio_read_write(struct mci_host *mci, struct mci_data *data)
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{
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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u32 blocks;
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char *buffer;
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u32 databuf;
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u32 size;
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u32 irqstat;
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u32 timeout;
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if (data->flags & MMC_DATA_READ) {
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blocks = data->blocks;
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buffer = data->dest;
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while (blocks) {
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timeout = PIO_TIMEOUT;
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size = data->blocksize;
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irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
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while (!(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_BREN)
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&& --timeout);
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if (timeout <= 0) {
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printf("\nData Read Failed in PIO Mode.");
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return;
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
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databuf = esdhc_read32(regs + SDHCI_BUFFER);
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*((u32 *)buffer) = databuf;
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buffer += 4;
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size -= 4;
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}
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blocks--;
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}
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} else {
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blocks = data->blocks;
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buffer = (char *)data->src;
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while (blocks) {
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timeout = PIO_TIMEOUT;
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size = data->blocksize;
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irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
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while (!(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_BWEN)
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&& --timeout);
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if (timeout <= 0) {
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printf("\nData Write Failed in PIO Mode.");
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return;
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}
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while (size && (!(irqstat & IRQSTAT_TC))) {
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udelay(100); /* Wait before last byte transfer complete */
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databuf = *((u32 *)buffer);
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buffer += 4;
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size -= 4;
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irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
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esdhc_write32(regs+ SDHCI_BUFFER, databuf);
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}
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blocks--;
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}
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}
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}
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#endif
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static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data)
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{
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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#ifndef CONFIG_MCI_IMX_ESDHC_PIO
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u32 wml_value;
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wml_value = data->blocksize/4;
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if (data->flags & MMC_DATA_READ) {
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if (wml_value > 0x10)
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wml_value = 0x10;
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esdhc_clrsetbits32(regs + IMX_SDHCI_WML, WML_RD_WML_MASK, wml_value);
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esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
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} else {
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if (wml_value > 0x80)
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wml_value = 0x80;
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if ((esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_WPSPL) == 0) {
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printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
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return -ETIMEDOUT;
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}
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esdhc_clrsetbits32(regs + IMX_SDHCI_WML, WML_WR_WML_MASK,
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wml_value << 16);
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esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->src);
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}
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#else /* CONFIG_MCI_IMX_ESDHC_PIO */
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if (!(data->flags & MMC_DATA_READ)) {
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if ((esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_WPSPL) == 0) {
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printf("\nThe SD card is locked. "
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"Can not write to a locked card.\n\n");
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return -ETIMEDOUT;
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}
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esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->src);
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} else
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esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)data->dest);
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#endif /* CONFIG_MCI_IMX_ESDHC_PIO */
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esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | data->blocksize);
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return 0;
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}
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/*
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* Sends a command out on the bus. Takes the mci pointer,
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* a command pointer, and an optional data pointer.
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*/
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static int
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esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
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{
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u32 xfertyp, mixctrl;
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u32 irqstat;
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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int ret;
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esdhc_write32(regs + SDHCI_INT_STATUS, -1);
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/* Wait at least 8 SD clock cycles before the next command */
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udelay(1);
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/* Set up for a data transfer if we have one */
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if (data) {
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int err;
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err = esdhc_setup_data(mci, data);
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if(err)
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return err;
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if (data->flags & MMC_DATA_WRITE) {
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dma_flush_range((unsigned long)data->src,
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(unsigned long)(data->src + data->blocks * 512));
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} else
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dma_clean_range((unsigned long)data->src,
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(unsigned long)(data->src + data->blocks * 512));
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}
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/* Figure out the transfer arguments */
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xfertyp = esdhc_xfertyp(cmd, data);
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/* Send the command */
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esdhc_write32(regs + SDHCI_ARGUMENT, cmd->cmdarg);
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if (cpu_is_mx6()) {
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/* write lower-half of xfertyp to mixctrl */
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mixctrl = xfertyp & 0xFFFF;
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/* Keep the bits 22-25 of the register as is */
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mixctrl |= (esdhc_read32(regs + IMX_SDHCI_MIXCTRL) & (0xF << 22));
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esdhc_write32(regs + IMX_SDHCI_MIXCTRL, mixctrl);
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}
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esdhc_write32(regs + SDHCI_TRANSFER_MODE__COMMAND, xfertyp);
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/* Wait for the command to complete */
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ret = wait_on_timeout(100 * MSECOND,
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esdhc_read32(regs + SDHCI_INT_STATUS) & IRQSTAT_CC);
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if (ret) {
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dev_dbg(host->dev, "timeout 1\n");
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return -ETIMEDOUT;
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}
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irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
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esdhc_write32(regs + SDHCI_INT_STATUS, irqstat);
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if (irqstat & CMD_ERR)
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return -EIO;
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if (irqstat & IRQSTAT_CTOE)
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return -ETIMEDOUT;
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/* Workaround for ESDHC errata ENGcm03648 / ENGcm12360 */
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if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
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/*
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* Poll on DATA0 line for cmd with busy signal for
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* timout / 10 usec since DLA polling can be insecure.
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*/
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ret = wait_on_timeout(2500 * MSECOND,
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(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_DAT0));
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if (ret) {
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dev_err(host->dev, "timeout PRSSTAT_DAT0\n");
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return -ETIMEDOUT;
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}
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}
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/* Copy the response to the response buffer */
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if (cmd->resp_type & MMC_RSP_136) {
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u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
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cmdrsp3 = esdhc_read32(regs + SDHCI_RESPONSE_3);
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cmdrsp2 = esdhc_read32(regs + SDHCI_RESPONSE_2);
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cmdrsp1 = esdhc_read32(regs + SDHCI_RESPONSE_1);
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cmdrsp0 = esdhc_read32(regs + SDHCI_RESPONSE_0);
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cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
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cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
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cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
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cmd->response[3] = (cmdrsp0 << 8);
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} else
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cmd->response[0] = esdhc_read32(regs + SDHCI_RESPONSE_0);
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/* Wait until all of the blocks are transferred */
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if (data) {
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#ifdef CONFIG_MCI_IMX_ESDHC_PIO
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esdhc_pio_read_write(mci, data);
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#else
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do {
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irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
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if (irqstat & DATA_ERR)
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return -EIO;
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if (irqstat & IRQSTAT_DTOE)
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return -ETIMEDOUT;
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} while (!(irqstat & IRQSTAT_TC) &&
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(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_DLA));
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if (data->flags & MMC_DATA_READ) {
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dma_inv_range((unsigned long)data->dest,
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(unsigned long)(data->dest + data->blocks * 512));
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}
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#endif
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}
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esdhc_write32(regs + SDHCI_INT_STATUS, -1);
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/* Wait for the bus to be idle */
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ret = wait_on_timeout(SECOND,
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!(esdhc_read32(regs + SDHCI_PRESENT_STATE) &
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(PRSSTAT_CICHB | PRSSTAT_CIDHB)));
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if (ret) {
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dev_err(host->dev, "timeout 2\n");
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return -ETIMEDOUT;
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}
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ret = wait_on_timeout(100 * MSECOND,
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!(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_DLA));
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if (ret) {
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dev_err(host->dev, "timeout 3\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void set_sysctl(struct mci_host *mci, u32 clock)
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{
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int div, pre_div;
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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int sdhc_clk = clk_get_rate(host->clk);
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u32 clk;
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unsigned long cur_clock;
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/*
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* With eMMC and imx53 (sdhc_clk=200MHz) a pre_div of 1 results in
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* pre_div=1,div=4 (=50MHz)
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* which is valid and should work, but somehow doesn't.
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* Starting with pre_div=2 gives
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* pre_div=2, div=2 (=50MHz)
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* and works fine.
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*/
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pre_div = 2;
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if (sdhc_clk == clock)
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pre_div = 1;
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else if (sdhc_clk / 16 > clock)
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for (; pre_div < 256; pre_div *= 2)
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if ((sdhc_clk / pre_div) <= (clock * 16))
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break;
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for (div = 1; div <= 16; div++)
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if ((sdhc_clk / (div * pre_div)) <= clock)
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break;
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cur_clock = sdhc_clk / pre_div / div;
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dev_dbg(host->dev, "set clock: wanted: %d got: %ld\n", clock, cur_clock);
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dev_dbg(host->dev, "pre_div: %d div: %d\n", pre_div, div);
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/* the register values start with 0 */
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div -= 1;
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pre_div >>= 1;
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clk = (pre_div << 8) | (div << 4);
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esdhc_clrbits32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
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SYSCTL_CKEN);
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esdhc_clrsetbits32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
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SYSCTL_CLOCK_MASK, clk);
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wait_on_timeout(10 * MSECOND,
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!(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_SDSTB));
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clk = SYSCTL_PEREN | SYSCTL_CKEN;
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esdhc_setbits32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
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clk);
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}
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static void esdhc_set_ios(struct mci_host *mci, struct mci_ios *ios)
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{
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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/* Set the clock speed */
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set_sysctl(mci, ios->clock);
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/* Set the bus width */
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esdhc_clrbits32(regs + SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
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PROCTL_DTW_4 | PROCTL_DTW_8);
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switch (ios->bus_width) {
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case MMC_BUS_WIDTH_4:
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esdhc_setbits32(regs + SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
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PROCTL_DTW_4);
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break;
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case MMC_BUS_WIDTH_8:
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esdhc_setbits32(regs + SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
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PROCTL_DTW_8);
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break;
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case MMC_BUS_WIDTH_1:
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break;
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default:
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return;
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}
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}
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static int esdhc_card_present(struct mci_host *mci)
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{
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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struct esdhc_platform_data *pdata = host->dev->platform_data;
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int ret;
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if (!pdata)
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return 1;
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switch (pdata->cd_type) {
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case ESDHC_CD_NONE:
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case ESDHC_CD_PERMANENT:
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return 1;
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case ESDHC_CD_CONTROLLER:
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return !(esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_WPSPL);
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case ESDHC_CD_GPIO:
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ret = gpio_direction_input(pdata->cd_gpio);
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if (ret)
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return ret;
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return gpio_get_value(pdata->cd_gpio) ? 0 : 1;
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}
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return 0;
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}
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static int esdhc_init(struct mci_host *mci, struct device_d *dev)
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{
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struct fsl_esdhc_host *host = to_fsl_esdhc(mci);
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void __iomem *regs = host->regs;
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int timeout = 1000;
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int ret = 0;
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/* Reset the entire host controller */
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esdhc_write32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
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SYSCTL_RSTA);
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/* Wait until the controller is available */
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while ((esdhc_read32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET)
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& SYSCTL_RSTA) && --timeout)
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udelay(1000);
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esdhc_write32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
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SYSCTL_HCKEN | SYSCTL_IPGEN);
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|
|
/* Set the initial clock speed */
|
|
set_sysctl(mci, 400000);
|
|
|
|
/* Disable the BRR and BWR bits in IRQSTAT */
|
|
esdhc_clrbits32(regs + SDHCI_INT_ENABLE, IRQSTATEN_BRR | IRQSTATEN_BWR);
|
|
|
|
/* Put the PROCTL reg back to the default */
|
|
esdhc_write32(regs + SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL,
|
|
PROCTL_INIT);
|
|
|
|
/* Set timout to the maximum value */
|
|
esdhc_clrsetbits32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
SYSCTL_TIMEOUT_MASK, 14 << 16);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int esdhc_reset(void __iomem *regs)
|
|
{
|
|
uint64_t start;
|
|
|
|
/* reset the controller */
|
|
esdhc_write32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET,
|
|
SYSCTL_RSTA);
|
|
|
|
start = get_time_ns();
|
|
/* hardware clears the bit when it is done */
|
|
while (1) {
|
|
if (!(esdhc_read32(regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET)
|
|
& SYSCTL_RSTA))
|
|
break;
|
|
if (is_timeout(start, 100 * MSECOND)) {
|
|
printf("MMC/SD: Reset never completed.\n");
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsl_esdhc_detect(struct device_d *dev)
|
|
{
|
|
struct fsl_esdhc_host *host = dev->priv;
|
|
|
|
return mci_detect_card(&host->mci);
|
|
}
|
|
|
|
static int fsl_esdhc_probe(struct device_d *dev)
|
|
{
|
|
struct fsl_esdhc_host *host;
|
|
struct mci_host *mci;
|
|
u32 caps;
|
|
int ret;
|
|
unsigned long rate;
|
|
struct esdhc_platform_data *pdata = dev->platform_data;
|
|
|
|
host = xzalloc(sizeof(*host));
|
|
mci = &host->mci;
|
|
|
|
host->clk = clk_get(dev, NULL);
|
|
if (IS_ERR(host->clk))
|
|
return PTR_ERR(host->clk);
|
|
|
|
host->dev = dev;
|
|
host->regs = dev_request_mem_region(dev, 0);
|
|
if (IS_ERR(host->regs))
|
|
return PTR_ERR(host->regs);
|
|
|
|
/* First reset the eSDHC controller */
|
|
ret = esdhc_reset(host->regs);
|
|
if (ret) {
|
|
free(host);
|
|
return ret;
|
|
}
|
|
|
|
caps = esdhc_read32(host->regs + SDHCI_CAPABILITIES);
|
|
|
|
if (caps & ESDHC_HOSTCAPBLT_VS18)
|
|
mci->voltages |= MMC_VDD_165_195;
|
|
if (caps & ESDHC_HOSTCAPBLT_VS30)
|
|
mci->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
|
if (caps & ESDHC_HOSTCAPBLT_VS33)
|
|
mci->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
if (pdata && pdata->caps)
|
|
mci->host_caps = pdata->caps;
|
|
else
|
|
mci->host_caps = MMC_CAP_4_BIT_DATA;
|
|
|
|
if (pdata && pdata->devname) {
|
|
mci->devname = pdata->devname;
|
|
} else if (dev->device_node) {
|
|
const char *alias = of_alias_get(dev->device_node);
|
|
if (alias)
|
|
mci->devname = xstrdup(alias);
|
|
}
|
|
|
|
if (caps & ESDHC_HOSTCAPBLT_HSS)
|
|
mci->host_caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
|
|
|
|
host->mci.send_cmd = esdhc_send_cmd;
|
|
host->mci.set_ios = esdhc_set_ios;
|
|
host->mci.init = esdhc_init;
|
|
host->mci.card_present = esdhc_card_present;
|
|
host->mci.hw_dev = dev;
|
|
|
|
dev->detect = fsl_esdhc_detect,
|
|
|
|
rate = clk_get_rate(host->clk);
|
|
host->mci.f_min = rate >> 12;
|
|
if (host->mci.f_min < 200000)
|
|
host->mci.f_min = 200000;
|
|
host->mci.f_max = rate;
|
|
if (pdata) {
|
|
host->mci.use_dsr = pdata->use_dsr;
|
|
host->mci.dsr_val = pdata->dsr_val;
|
|
}
|
|
|
|
mci_of_parse(&host->mci);
|
|
|
|
dev->priv = host;
|
|
|
|
return mci_register(&host->mci);
|
|
}
|
|
|
|
static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = {
|
|
{
|
|
.compatible = "fsl,imx25-esdhc",
|
|
}, {
|
|
.compatible = "fsl,imx51-esdhc",
|
|
}, {
|
|
.compatible = "fsl,imx53-esdhc",
|
|
}, {
|
|
.compatible = "fsl,imx6q-usdhc",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct driver_d fsl_esdhc_driver = {
|
|
.name = "imx-esdhc",
|
|
.probe = fsl_esdhc_probe,
|
|
.of_compatible = DRV_OF_COMPAT(fsl_esdhc_compatible),
|
|
};
|
|
device_platform_driver(fsl_esdhc_driver);
|