bd1bf53b34
This gives the SDHCI specific registers a common name and moves them to a separate file for use by other SDHCI like drivers. The SDHCI spec has some 16bit and 8bit registers. The i.MX accesses these as 32bit registers. These register defines now are named after the SDHCI registers they combine into one, for example: SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL is the 32bit version of the SDHCI registers HOST_CONTROL, POWER_CONTROL and BLOCK_GAP_CONTROL. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
71 lines
2.1 KiB
C
71 lines
2.1 KiB
C
/*
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* FSL SD/MMC Defines
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*-------------------------------------------------------------------
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*
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* Copyright 2007-2008,2010 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*-------------------------------------------------------------------
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*
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*/
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#ifndef __FSL_ESDHC_H__
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#define __FSL_ESDHC_H__
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#include <errno.h>
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#include <asm/byteorder.h>
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#define SYSCTL_INITA 0x08000000
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#define SYSCTL_TIMEOUT_MASK 0x000f0000
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#define SYSCTL_CLOCK_MASK 0x0000fff0
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#define SYSCTL_RSTA 0x01000000
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#define SYSCTL_CKEN 0x00000008
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#define SYSCTL_PEREN 0x00000004
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#define SYSCTL_HCKEN 0x00000002
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#define SYSCTL_IPGEN 0x00000001
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#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
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#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
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#define PROCTL_INIT 0x00000020
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#define PROCTL_DTW_4 0x00000002
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#define PROCTL_DTW_8 0x00000004
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#define WML_WRITE 0x00010000
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#define WML_RD_WML_MASK 0xff
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#define WML_WR_WML_MASK 0xff0000
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#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
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#define BLKATTR_SIZE(x) (x & 0x1fff)
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#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
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#define ESDHC_HOSTCAPBLT_VS18 0x04000000
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#define ESDHC_HOSTCAPBLT_VS30 0x02000000
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#define ESDHC_HOSTCAPBLT_VS33 0x01000000
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#define ESDHC_HOSTCAPBLT_SRS 0x00800000
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#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
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#define ESDHC_HOSTCAPBLT_HSS 0x00200000
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struct fsl_esdhc_cfg {
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u32 esdhc_base;
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u32 no_snoop;
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};
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#define esdhc_read32(a) readl(a)
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#define esdhc_write32(a, v) writel(v,a)
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#define esdhc_clrsetbits32(a, c, s) writel((readl(a) & ~(c)) | (s), (a))
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#define esdhc_clrbits32(a, c) writel(readl(a) & ~(c), (a))
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#define esdhc_setbits32(a, s) writel(readl(a) | (s), (a))
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#endif /* __FSL_ESDHC_H__ */
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