For all users fix or add the error check. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
671 lines
17 KiB
C
671 lines
17 KiB
C
/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Sukumar Ghorai <s-ghorai@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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/* #define DEBUG */
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#include <config.h>
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <mci.h>
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#include <clock.h>
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#include <errno.h>
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#include <io.h>
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#include <linux/err.h>
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#include <mach/omap_hsmmc.h>
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#if defined(CONFIG_MFD_TWL6030) && \
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defined(CONFIG_MCI_OMAP_HSMMC) && \
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defined(CONFIG_ARCH_OMAP4)
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#include <mach/omap4_twl6030_mmc.h>
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#endif
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struct hsmmc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int sysstatus; /* 0x14 */
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unsigned char res2[0x14];
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unsigned int con; /* 0x2C */
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unsigned char res3[0xD4];
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unsigned int blk; /* 0x104 */
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unsigned int arg; /* 0x108 */
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unsigned int cmd; /* 0x10C */
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unsigned int rsp10; /* 0x110 */
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unsigned int rsp32; /* 0x114 */
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unsigned int rsp54; /* 0x118 */
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unsigned int rsp76; /* 0x11C */
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unsigned int data; /* 0x120 */
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unsigned int pstate; /* 0x124 */
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unsigned int hctl; /* 0x128 */
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unsigned int sysctl; /* 0x12C */
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unsigned int stat; /* 0x130 */
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unsigned int ie; /* 0x134 */
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unsigned char res4[0x8];
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unsigned int capa; /* 0x140 */
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};
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struct omap_mmc_driver_data {
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unsigned long reg_ofs;
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};
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static struct omap_mmc_driver_data omap3_data = {
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.reg_ofs = 0,
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};
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static struct omap_mmc_driver_data omap4_data = {
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.reg_ofs = 0x100,
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};
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/*
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* OMAP HS MMC Bit definitions
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*/
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#define MMC_SOFTRESET (0x1 << 1)
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#define RESETDONE (0x1 << 0)
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#define NOOPENDRAIN (0x0 << 0)
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#define OPENDRAIN (0x1 << 0)
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#define OD (0x1 << 0)
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#define INIT_NOINIT (0x0 << 1)
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#define INIT_INITSTREAM (0x1 << 1)
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#define HR_NOHOSTRESP (0x0 << 2)
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#define STR_BLOCK (0x0 << 3)
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#define MODE_FUNC (0x0 << 4)
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#define DW8_1_4BITMODE (0x0 << 5)
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#define MIT_CTO (0x0 << 6)
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#define CDP_ACTIVEHIGH (0x0 << 7)
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#define WPP_ACTIVEHIGH (0x0 << 8)
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#define RESERVED_MASK (0x3 << 9)
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#define CTPL_MMC_SD (0x0 << 11)
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#define BLEN_512BYTESLEN (0x200 << 0)
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#define NBLK_STPCNT (0x0 << 16)
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#define DE_DISABLE (0x0 << 0)
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#define BCE_DISABLE (0x0 << 1)
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#define BCE_ENABLE (0x1 << 1)
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#define ACEN_DISABLE (0x0 << 2)
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#define DDIR_OFFSET (4)
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#define DDIR_MASK (0x1 << 4)
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#define DDIR_WRITE (0x0 << 4)
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#define DDIR_READ (0x1 << 4)
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#define MSBS_SGLEBLK (0x0 << 5)
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#define MSBS_MULTIBLK (0x1 << 5)
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#define RSP_TYPE_OFFSET (16)
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#define RSP_TYPE_MASK (0x3 << 16)
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#define RSP_TYPE_NORSP (0x0 << 16)
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#define RSP_TYPE_LGHT136 (0x1 << 16)
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#define RSP_TYPE_LGHT48 (0x2 << 16)
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#define RSP_TYPE_LGHT48B (0x3 << 16)
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#define CCCE_NOCHECK (0x0 << 19)
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#define CCCE_CHECK (0x1 << 19)
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#define CICE_NOCHECK (0x0 << 20)
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#define CICE_CHECK (0x1 << 20)
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#define DP_OFFSET (21)
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#define DP_MASK (0x1 << 21)
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#define DP_NO_DATA (0x0 << 21)
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#define DP_DATA (0x1 << 21)
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#define CMD_TYPE_NORMAL (0x0 << 22)
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#define INDEX_OFFSET (24)
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#define INDEX_MASK (0x3f << 24)
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#define INDEX(i) (i << 24)
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#define DATI_MASK (0x1 << 1)
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#define DATI_CMDDIS (0x1 << 1)
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#define DTW_1_BITMODE (0x0 << 1)
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#define DTW_4_BITMODE (0x1 << 1)
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#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
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#define SDBP_PWROFF (0x0 << 8)
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#define SDBP_PWRON (0x1 << 8)
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#define SDVS_1V8 (0x5 << 9)
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#define SDVS_3V0 (0x6 << 9)
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#define ICE_MASK (0x1 << 0)
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#define ICE_STOP (0x0 << 0)
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#define ICS_MASK (0x1 << 1)
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#define ICS_NOTREADY (0x0 << 1)
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#define ICE_OSCILLATE (0x1 << 0)
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#define CEN_MASK (0x1 << 2)
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#define CEN_DISABLE (0x0 << 2)
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#define CEN_ENABLE (0x1 << 2)
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#define CLKD_OFFSET (6)
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#define CLKD_MASK (0x3FF << 6)
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#define DTO_MASK (0xF << 16)
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#define DTO_15THDTO (0xE << 16)
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#define SOFTRESETALL (0x1 << 24)
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#define CC_MASK (0x1 << 0)
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#define TC_MASK (0x1 << 1)
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#define BWR_MASK (0x1 << 4)
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#define BRR_MASK (0x1 << 5)
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#define ERRI_MASK (0x1 << 15)
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#define IE_CC (0x01 << 0)
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#define IE_TC (0x01 << 1)
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#define IE_BWR (0x01 << 4)
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#define IE_BRR (0x01 << 5)
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#define IE_CTO (0x01 << 16)
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#define IE_CCRC (0x01 << 17)
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#define IE_CEB (0x01 << 18)
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#define IE_CIE (0x01 << 19)
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#define IE_DTO (0x01 << 20)
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#define IE_DCRC (0x01 << 21)
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#define IE_DEB (0x01 << 22)
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#define IE_CERR (0x01 << 28)
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#define IE_BADA (0x01 << 29)
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#define VS30_3V0SUP (1 << 25)
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#define VS18_1V8SUP (1 << 26)
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/* Driver definitions */
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#define MMCSD_SECTOR_SIZE 512
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#define MMC_CARD 0
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#define SD_CARD 1
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#define BYTE_MODE 0
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#define SECTOR_MODE 1
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#define CLK_INITSEQ 0
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#define CLK_400KHZ 1
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#define CLK_MISC 2
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#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
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#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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/* Clock Configurations and Macros */
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#define MMC_CLOCK_REFERENCE 96 /* MHz */
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#define mmc_reg_out(addr, mask, val)\
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writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
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struct omap_hsmmc {
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struct mci_host mci;
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struct device_d *dev;
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struct hsmmc *base;
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void __iomem *iobase;
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};
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#define to_hsmmc(mci) container_of(mci, struct omap_hsmmc, mci)
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static int mmc_init_stream(struct omap_hsmmc *hsmmc)
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{
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uint64_t start;
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struct hsmmc *mmc_base = hsmmc->base;
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writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
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writel(MMC_CMD0, &mmc_base->cmd);
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start = get_time_ns();
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while (!(readl(&mmc_base->stat) & CC_MASK)) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for cc!\n");
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return -ETIMEDOUT;
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}
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}
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writel(CC_MASK, &mmc_base->stat);
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writel(MMC_CMD0, &mmc_base->cmd);
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start = get_time_ns();
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while (!(readl(&mmc_base->stat) & CC_MASK)) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for cc2!\n");
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return -ETIMEDOUT;
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}
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}
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writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
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return 0;
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}
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static int mmc_init_setup(struct mci_host *mci, struct device_d *dev)
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{
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struct omap_hsmmc *hsmmc = to_hsmmc(mci);
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struct hsmmc *mmc_base = hsmmc->base;
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unsigned int reg_val;
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unsigned int dsor;
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uint64_t start;
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/*
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* Fix voltage for mmc, if booting from nand.
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* It's necessary to do this here, because
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* you need to set up this at probetime.
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*/
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#if defined(CONFIG_MFD_TWL6030) && \
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defined(CONFIG_MCI_OMAP_HSMMC) && \
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defined(CONFIG_ARCH_OMAP4)
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set_up_mmc_voltage_omap4();
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#endif
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writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
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&mmc_base->sysconfig);
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start = get_time_ns();
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while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timeout waiting for reset done\n");
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return -ETIMEDOUT;
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}
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}
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writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
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start = get_time_ns();
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while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for softresetall!\n");
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return -ETIMEDOUT;
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}
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}
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writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
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writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
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&mmc_base->capa);
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reg_val = readl(&mmc_base->con) & RESERVED_MASK;
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writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
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MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
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HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
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dsor = 240;
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mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
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(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
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mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
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(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
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start = get_time_ns();
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while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for ics!\n");
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return -ETIMEDOUT;
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}
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}
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writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
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writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
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writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
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IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
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&mmc_base->ie);
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return mmc_init_stream(hsmmc);
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}
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static int mmc_read_data(struct omap_hsmmc *hsmmc, char *buf, unsigned int size)
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{
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struct hsmmc *mmc_base = hsmmc->base;
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unsigned int *output_buf = (unsigned int *)buf;
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unsigned int mmc_stat;
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unsigned int count;
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/*
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* Start Polled Read
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*/
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count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
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count /= 4;
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while (size) {
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uint64_t start = get_time_ns();
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do {
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mmc_stat = readl(&mmc_base->stat);
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for status!\n");
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return -ETIMEDOUT;
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}
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return 1;
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if (mmc_stat & BRR_MASK) {
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unsigned int k;
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writel(readl(&mmc_base->stat) | BRR_MASK,
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&mmc_base->stat);
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for (k = 0; k < count; k++) {
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*output_buf = readl(&mmc_base->data);
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output_buf++;
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}
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size -= (count*4);
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}
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if (mmc_stat & BWR_MASK)
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writel(readl(&mmc_base->stat) | BWR_MASK,
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&mmc_base->stat);
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if (mmc_stat & TC_MASK) {
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writel(readl(&mmc_base->stat) | TC_MASK,
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&mmc_base->stat);
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break;
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}
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}
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return 0;
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}
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#ifdef CONFIG_MCI_WRITE
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static int mmc_write_data(struct omap_hsmmc *hsmmc, const char *buf, unsigned int size)
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{
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struct hsmmc *mmc_base = hsmmc->base;
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unsigned int *input_buf = (unsigned int *)buf;
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unsigned int mmc_stat;
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unsigned int count;
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/*
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* Start Polled Read
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*/
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count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
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count /= 4;
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while (size) {
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uint64_t start = get_time_ns();
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do {
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mmc_stat = readl(&mmc_base->stat);
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for status!\n");
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return -ETIMEDOUT;
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}
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} while (mmc_stat == 0);
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if ((mmc_stat & ERRI_MASK) != 0)
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return 1;
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if (mmc_stat & BWR_MASK) {
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unsigned int k;
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writel(readl(&mmc_base->stat) | BWR_MASK,
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&mmc_base->stat);
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for (k = 0; k < count; k++) {
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writel(*input_buf, &mmc_base->data);
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input_buf++;
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}
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size -= (count * 4);
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}
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if (mmc_stat & BRR_MASK)
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writel(readl(&mmc_base->stat) | BRR_MASK,
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&mmc_base->stat);
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if (mmc_stat & TC_MASK) {
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writel(readl(&mmc_base->stat) | TC_MASK,
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&mmc_base->stat);
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break;
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}
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}
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return 0;
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}
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#endif
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static int mmc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
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struct mci_data *data)
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{
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struct omap_hsmmc *hsmmc = to_hsmmc(mci);
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struct hsmmc *mmc_base = hsmmc->base;
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unsigned int flags, mmc_stat;
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uint64_t start;
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start = get_time_ns();
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while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for cmddis!\n");
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return -ETIMEDOUT;
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}
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}
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writel(0xFFFFFFFF, &mmc_base->stat);
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start = get_time_ns();
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while (readl(&mmc_base->stat)) {
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if (is_timeout(start, SECOND)) {
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dev_dbg(hsmmc->dev, "timedout waiting for stat!\n");
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return -ETIMEDOUT;
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}
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}
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/*
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* CMDREG
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* CMDIDX[13:8] : Command index
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* DATAPRNT[5] : Data Present Select
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* ENCMDIDX[4] : Command Index Check Enable
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* ENCMDCRC[3] : Command CRC Check Enable
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* RSPTYP[1:0]
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* 00 = No Response
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* 01 = Length 136
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* 10 = Length 48
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* 11 = Length 48 Check busy after response
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*/
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/* Delay added before checking the status of frq change
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* retry not supported by mmc.c(core file)
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*/
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if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
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udelay(50000); /* wait 50 ms */
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = 0;
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else if (cmd->resp_type & MMC_RSP_136)
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flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = RSP_TYPE_LGHT48B;
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else
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flags = RSP_TYPE_LGHT48;
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/* enable default flags */
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flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
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MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= CCCE_CHECK;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= CICE_CHECK;
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if (data) {
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if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
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(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
|
|
flags |= (MSBS_MULTIBLK | BCE_ENABLE);
|
|
data->blocksize = 512;
|
|
writel(data->blocksize | (data->blocks << 16),
|
|
&mmc_base->blk);
|
|
} else
|
|
writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
flags |= (DP_DATA | DDIR_READ);
|
|
else
|
|
flags |= (DP_DATA | DDIR_WRITE);
|
|
}
|
|
|
|
writel(cmd->cmdarg, &mmc_base->arg);
|
|
writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
|
|
|
|
start = get_time_ns();
|
|
do {
|
|
mmc_stat = readl(&mmc_base->stat);
|
|
if (is_timeout(start, SECOND)) {
|
|
dev_dbg(hsmmc->dev, "timeout: No status update\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
} while (!mmc_stat);
|
|
|
|
if ((mmc_stat & IE_CTO) != 0)
|
|
return -ETIMEDOUT;
|
|
else if ((mmc_stat & ERRI_MASK) != 0)
|
|
return -1;
|
|
|
|
if (mmc_stat & CC_MASK) {
|
|
writel(CC_MASK, &mmc_base->stat);
|
|
if (cmd->resp_type & MMC_RSP_PRESENT) {
|
|
if (cmd->resp_type & MMC_RSP_136) {
|
|
/* response type 2 */
|
|
cmd->response[3] = readl(&mmc_base->rsp10);
|
|
cmd->response[2] = readl(&mmc_base->rsp32);
|
|
cmd->response[1] = readl(&mmc_base->rsp54);
|
|
cmd->response[0] = readl(&mmc_base->rsp76);
|
|
} else
|
|
/* response types 1, 1b, 3, 4, 5, 6 */
|
|
cmd->response[0] = readl(&mmc_base->rsp10);
|
|
}
|
|
}
|
|
|
|
if (data && (data->flags & MMC_DATA_READ))
|
|
mmc_read_data(hsmmc, data->dest, data->blocksize * data->blocks);
|
|
#ifdef CONFIG_MCI_WRITE
|
|
else if (data && (data->flags & MMC_DATA_WRITE))
|
|
mmc_write_data(hsmmc, data->src, data->blocksize * data->blocks);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static void mmc_set_ios(struct mci_host *mci, struct mci_ios *ios)
|
|
{
|
|
struct omap_hsmmc *hsmmc = to_hsmmc(mci);
|
|
struct hsmmc *mmc_base = hsmmc->base;
|
|
unsigned int dsor = 0;
|
|
uint64_t start;
|
|
|
|
/* configue bus width */
|
|
switch (ios->bus_width) {
|
|
case MMC_BUS_WIDTH_8:
|
|
writel(readl(&mmc_base->con) | DTW_8_BITMODE,
|
|
&mmc_base->con);
|
|
break;
|
|
|
|
case MMC_BUS_WIDTH_4:
|
|
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
|
|
&mmc_base->con);
|
|
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
|
|
&mmc_base->hctl);
|
|
break;
|
|
|
|
case MMC_BUS_WIDTH_1:
|
|
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
|
|
&mmc_base->con);
|
|
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
|
|
&mmc_base->hctl);
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
/* configure clock with 96Mhz system clock.
|
|
*/
|
|
if (ios->clock != 0) {
|
|
dsor = (MMC_CLOCK_REFERENCE * 1000000 / ios->clock);
|
|
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > ios->clock)
|
|
dsor++;
|
|
}
|
|
|
|
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
|
|
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
|
|
|
|
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
|
|
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
|
|
|
|
start = get_time_ns();
|
|
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
|
|
if (is_timeout(start, SECOND)) {
|
|
dev_dbg(hsmmc->dev, "timedout waiting for ics!\n");
|
|
return;
|
|
}
|
|
}
|
|
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
|
|
}
|
|
|
|
static int omap_mmc_detect(struct device_d *dev)
|
|
{
|
|
struct omap_hsmmc *hsmmc = dev->priv;
|
|
|
|
return mci_detect_card(&hsmmc->mci);
|
|
}
|
|
|
|
static int omap_mmc_probe(struct device_d *dev)
|
|
{
|
|
struct omap_hsmmc *hsmmc;
|
|
struct omap_hsmmc_platform_data *pdata;
|
|
struct omap_mmc_driver_data *drvdata;
|
|
unsigned long reg_ofs = 0;
|
|
int ret;
|
|
|
|
ret = dev_get_drvdata(dev, (unsigned long *)&drvdata);
|
|
if (!ret)
|
|
reg_ofs = drvdata->reg_ofs;
|
|
|
|
hsmmc = xzalloc(sizeof(*hsmmc));
|
|
|
|
hsmmc->dev = dev;
|
|
hsmmc->mci.send_cmd = mmc_send_cmd;
|
|
hsmmc->mci.set_ios = mmc_set_ios;
|
|
hsmmc->mci.init = mmc_init_setup;
|
|
hsmmc->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED |
|
|
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_8_BIT_DATA;
|
|
hsmmc->mci.hw_dev = dev;
|
|
|
|
hsmmc->iobase = dev_request_mem_region(dev, 0);
|
|
if (IS_ERR(hsmmc->iobase))
|
|
return PTR_ERR(hsmmc->iobase);
|
|
hsmmc->base = hsmmc->iobase + reg_ofs;
|
|
|
|
hsmmc->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
hsmmc->mci.f_min = 400000;
|
|
hsmmc->mci.f_max = 52000000;
|
|
|
|
pdata = (struct omap_hsmmc_platform_data *)dev->platform_data;
|
|
if (pdata) {
|
|
if (pdata->f_max)
|
|
hsmmc->mci.f_max = pdata->f_max;
|
|
|
|
if (pdata->devname)
|
|
hsmmc->mci.devname = pdata->devname;
|
|
}
|
|
|
|
if (dev->device_node) {
|
|
const char *alias = of_alias_get(dev->device_node);
|
|
if (alias)
|
|
hsmmc->mci.devname = xstrdup(alias);
|
|
}
|
|
|
|
dev->priv = hsmmc;
|
|
dev->detect = omap_mmc_detect,
|
|
|
|
mci_register(&hsmmc->mci);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_device_id omap_mmc_ids[] = {
|
|
{
|
|
.name = "omap3-hsmmc",
|
|
.driver_data = (unsigned long)&omap3_data,
|
|
}, {
|
|
.name = "omap4-hsmmc",
|
|
.driver_data = (unsigned long)&omap4_data,
|
|
}, {
|
|
/* sentinel */
|
|
},
|
|
};
|
|
|
|
static __maybe_unused struct of_device_id omap_mmc_dt_ids[] = {
|
|
{
|
|
.compatible = "ti,omap3-hsmmc",
|
|
.data = (unsigned long)&omap3_data,
|
|
}, {
|
|
.compatible = "ti,omap4-hsmmc",
|
|
.data = (unsigned long)&omap4_data,
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct driver_d omap_mmc_driver = {
|
|
.name = "omap-hsmmc",
|
|
.probe = omap_mmc_probe,
|
|
.id_table = omap_mmc_ids,
|
|
.of_compatible = DRV_OF_COMPAT(omap_mmc_dt_ids),
|
|
};
|
|
device_platform_driver(omap_mmc_driver);
|