e3ab3078dc
At least i.MX53 has errata ENGcm12360: Occurs when a pending command which issues busy is completed. For a command with R1b response, the proper software sequence is to poll the DLA for R1b commands to determine busy state completion. The DLA polling is not working properly for the ESDHC module. This is relevant for all eSDHC ports (eSDHC1-4 ports) DLA bit in PRSSTAT register cannot be polled to wait for busy state completion. Updated block guide to reflect that DLA is not applicable to detect busy state, instead, should poll bit 24 in PRSSTAT register (DLSL[0] bit) to check that wait busy state is over. Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
93 lines
3 KiB
C
93 lines
3 KiB
C
#ifndef __MCI_SDHCI_H
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#define __MCI_SDHCI_H
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE__BLOCK_COUNT 0x04
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE__COMMAND 0x0c
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#define SDHCI_RESPONSE_0 0x10
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#define SDHCI_RESPONSE_1 0x14
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#define SDHCI_RESPONSE_2 0x18
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#define SDHCI_RESPONSE_3 0x1c
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_HOST_CONTROL__POWER_CONTROL__BLOCK_GAP_CONTROL 0x28
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#define SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET 0x2c
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_ACMD12_ERR__HOST_CONTROL2 0x3C
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#define SDHCI_CAPABILITIES 0x40
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#define COMMAND_CMD(x) ((x & 0x3f) << 24)
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#define COMMAND_CMDTYP_NORMAL 0x0
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#define COMMAND_CMDTYP_SUSPEND 0x00400000
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#define COMMAND_CMDTYP_RESUME 0x00800000
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#define COMMAND_CMDTYP_ABORT 0x00c00000
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#define COMMAND_DPSEL 0x00200000
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#define COMMAND_CICEN 0x00100000
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#define COMMAND_CCCEN 0x00080000
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#define COMMAND_RSPTYP_NONE 0
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#define COMMAND_RSPTYP_136 0x00010000
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#define COMMAND_RSPTYP_48 0x00020000
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#define COMMAND_RSPTYP_48_BUSY 0x00030000
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#define TRANSFER_MODE_MSBSEL 0x00000020
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#define TRANSFER_MODE_DTDSEL 0x00000010
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#define TRANSFER_MODE_AC12EN 0x00000004
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#define TRANSFER_MODE_BCEN 0x00000002
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#define TRANSFER_MODE_DMAEN 0x00000001
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#define IRQSTAT_TE 0x04000000
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#define IRQSTAT_DMAE 0x02000000
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#define IRQSTAT_AC12E 0x01000000
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#define IRQSTAT_CLE 0x00800000
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#define IRQSTAT_DEBE 0x00400000
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#define IRQSTAT_DCE 0x00200000
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#define IRQSTAT_DTOE 0x00100000
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#define IRQSTAT_CIE 0x00080000
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#define IRQSTAT_CEBE 0x00040000
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#define IRQSTAT_CCE 0x00020000
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#define IRQSTAT_CTOE 0x00010000
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#define IRQSTAT_CINT 0x00000100
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#define IRQSTAT_CRM 0x00000080
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#define IRQSTAT_CINS 0x00000040
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#define IRQSTAT_BRR 0x00000020
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#define IRQSTAT_BWR 0x00000010
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#define IRQSTAT_DINT 0x00000008
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#define IRQSTAT_BGE 0x00000004
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#define IRQSTAT_TC 0x00000002
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#define IRQSTAT_CC 0x00000001
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#define IRQSTATEN_DMAE 0x10000000
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#define IRQSTATEN_AC12E 0x01000000
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#define IRQSTATEN_DEBE 0x00400000
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#define IRQSTATEN_DCE 0x00200000
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#define IRQSTATEN_DTOE 0x00100000
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#define IRQSTATEN_CIE 0x00080000
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#define IRQSTATEN_CEBE 0x00040000
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#define IRQSTATEN_CCE 0x00020000
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#define IRQSTATEN_CTOE 0x00010000
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#define IRQSTATEN_CINT 0x00000100
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#define IRQSTATEN_CRM 0x00000080
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#define IRQSTATEN_CINS 0x00000040
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#define IRQSTATEN_BRR 0x00000020
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#define IRQSTATEN_BWR 0x00000010
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#define IRQSTATEN_DINT 0x00000008
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#define IRQSTATEN_BGE 0x00000004
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#define IRQSTATEN_TC 0x00000002
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#define IRQSTATEN_CC 0x00000001
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#define PRSSTAT_DAT0 0x01000000
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#define PRSSTAT_CLSL 0x00800000
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#define PRSSTAT_WPSPL 0x00080000
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#define PRSSTAT_CDPL 0x00040000
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#define PRSSTAT_CINS 0x00010000
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#define PRSSTAT_BREN 0x00000800
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#define PRSSTAT_BWEN 0x00000400
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#define PRSSTAT_SDSTB 0x00000008
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#define PRSSTAT_DLA 0x00000004
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#define PRSSTAT_CIDHB 0x00000002
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#define PRSSTAT_CICHB 0x00000001
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#endif /* __MCI_SDHCI_H */
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