The pxamci requires a bit to be set in the command control register when a CMD12 is sent. Set it, as required in the PXA Developer Manuel, chapter "Stop Data Transmission Command (CMD12 or IO/Abort with CMD52)". Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
101 lines
2.8 KiB
C
101 lines
2.8 KiB
C
/*
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* PXA MCI driver
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*
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* Copyright (C) 2011 Robert Jarzmik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Insprired by linux kernel driver
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*/
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#define MMC_FIFO_LENGTH 32
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#define MMC_STRPCL 0x0000
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#define STOP_CLOCK (1 << 0)
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#define START_CLOCK (2 << 0)
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#define MMC_STAT 0x0004
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#define STAT_END_CMD_RES (1 << 13)
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#define STAT_PRG_DONE (1 << 12)
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#define STAT_DATA_TRAN_DONE (1 << 11)
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#define STAT_CLK_EN (1 << 8)
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#define STAT_RECV_FIFO_FULL (1 << 7)
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#define STAT_XMIT_FIFO_EMPTY (1 << 6)
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#define STAT_RES_CRC_ERR (1 << 5)
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#define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
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#define STAT_CRC_READ_ERROR (1 << 3)
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#define STAT_CRC_WRITE_ERROR (1 << 2)
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#define STAT_TIME_OUT_RESPONSE (1 << 1)
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#define STAT_READ_TIME_OUT (1 << 0)
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#define MMC_CLKRT 0x0008 /* 3 bit */
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#define MMC_SPI 0x000c
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#define SPI_CS_ADDRESS (1 << 3)
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#define SPI_CS_EN (1 << 2)
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#define CRC_ON (1 << 1)
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#define SPI_EN (1 << 0)
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#define MMC_CMDAT 0x0010
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#define CMDAT_SDIO_INT_EN (1 << 11)
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#define CMDAT_STOP_TRAN (1 << 10)
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#define CMDAT_SD_4DAT (1 << 8)
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#define CMDAT_DMAEN (1 << 7)
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#define CMDAT_INIT (1 << 6)
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#define CMDAT_BUSY (1 << 5)
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#define CMDAT_STREAM (1 << 4) /* 1 = stream */
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#define CMDAT_WRITE (1 << 3) /* 1 = write */
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#define CMDAT_DATAEN (1 << 2)
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#define CMDAT_RESP_NONE (0 << 0)
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#define CMDAT_RESP_SHORT (1 << 0)
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#define CMDAT_RESP_R2 (2 << 0)
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#define CMDAT_RESP_R3 (3 << 0)
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#define MMC_RESTO 0x0014 /* 7 bit */
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#define MMC_RDTO 0x0018 /* 16 bit */
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#define MMC_BLKLEN 0x001c /* 10 bit */
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#define MMC_NOB 0x0020 /* 16 bit */
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#define MMC_PRTBUF 0x0024
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#define BUF_PART_FULL (1 << 0)
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#define MMC_I_REG 0x002c
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#define TXFIFO_WR_REQ (1 << 6)
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#define RXFIFO_RD_REQ (1 << 5)
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#define CLK_IS_OFF (1 << 4)
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#define STOP_CMD (1 << 3)
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#define END_CMD_RES (1 << 2)
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#define PRG_DONE (1 << 1)
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#define DATA_TRAN_DONE (1 << 0)
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#define MMC_I_MASK 0x0028
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#define MMC_CMD 0x0030
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#define MMC_ARGH 0x0034 /* 16 bit */
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#define MMC_ARGL 0x0038 /* 16 bit */
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#define MMC_RES 0x003c /* 16 bit */
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#define MMC_RXFIFO 0x0040 /* 8 bit */
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#define MMC_TXFIFO 0x0044 /* 8 bit */
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struct pxamci_host {
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struct mci_host mci;
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void __iomem *base;
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struct pxamci_platform_data *pdata;
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unsigned int cmdat;
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int clkrt;
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};
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#define to_pxamci(mci) container_of(mci, struct pxamci_host, mci)
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#define mmc_readb(reg) readb(host->base + (reg))
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#define mmc_readl(reg) readl(host->base + (reg))
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#define mmc_writeb(val, reg) writeb((val), host->base + (reg))
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#define mmc_writel(val, reg) writel((val), host->base + (reg))
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#define mci_dbg(fmt, arg...) \
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dev_dbg(host->mci.hw_dev, "%s: " fmt, __func__, ## arg)
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#define mci_err(fmt, arg...) \
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dev_err(host->mci.hw_dev, "%s: " fmt, __func__, ## arg)
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