This adds a pinctrl driver for the Tegra 20 line of SoCs. It only supports the three basic pinconfiguration settings function mux, tristate control and pullup/down control. The driver understands the same devicetree bindings as the Linux one, unimplemented pinconfiguration options will be ignored. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
347 lines
14 KiB
C
347 lines
14 KiB
C
/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* Partly based on code
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* Copyright (C) 2011-2012 NVIDIA Corporation <www.nvidia.com>
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* Copyright (C) 2010 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief Device driver for the Tegra 20 pincontrol hardware module.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <malloc.h>
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#include <pinctrl.h>
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struct pinctrl_tegra20 {
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struct {
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u32 __iomem *tri;
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u32 __iomem *mux;
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u32 __iomem *pull;
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} regs;
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struct pinctrl_device pinctrl;
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};
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struct tegra20_pingroup {
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const char *name;
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const char *funcs[4];
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s16 trictrl_id;
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s16 muxctrl_id;
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s16 pullctrl_id;
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};
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#define PG(pg_name, f0, f1, f2, f3, tri, mux, pull) \
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{ \
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.name = #pg_name, \
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.funcs = { #f0, #f1, #f2, #f3, }, \
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.trictrl_id = tri, \
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.muxctrl_id = mux, \
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.pullctrl_id = pull \
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}
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static const struct tegra20_pingroup tegra20_groups[] = {
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/* name, f0, f1, f2, f3, tri, mux, pull */
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PG(ata, ide, nand, gmi, rsvd4, 0, 12, 0 ),
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PG(atb, ide, nand, gmi, sdio4, 1, 8, 1 ),
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PG(atc, ide, nand, gmi, sdio4, 2, 11, 2 ),
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PG(atd, ide, nand, gmi, sdio4, 3, 10, 3 ),
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PG(ate, ide, nand, gmi, rsvd4, 57, 6, 4 ),
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PG(cdev1, osc, plla_out, pllm_out1, audio_sync, 4, 33, 32 ),
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PG(cdev2, osc, ahb_clk, apb_clk, pllp_out4, 5, 34, 33 ),
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PG(crtp, crt, rsvd2, rsvd3, rsvd4, 110, 105, 28 ),
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PG(csus, pllc_out1, pllp_out2, pllp_out3, vi_sensor_clk, 6, 35, 60 ),
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PG(dap1, dap1, rsvd2, gmi, sdio2, 7, 42, 5 ),
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PG(dap2, dap2, twc, rsvd3, gmi, 8, 43, 6 ),
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PG(dap3, dap3, rsvd2, rsvd3, rsvd4, 9, 44, 7 ),
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PG(dap4, dap4, rsvd2, gmi, rsvd4, 10, 45, 8 ),
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PG(ddc, i2c2, rsvd2, rsvd3, rsvd4, 63, 32, 78 ),
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PG(dta, rsvd1, sdio2, vi, rsvd4, 11, 26, 9 ),
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PG(dtb, rsvd1, rsvd2, vi, spi1, 12, 27, 10 ),
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PG(dtc, rsvd1, rsvd2, vi, rsvd4, 13, 29, 11 ),
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PG(dtd, rsvd1, sdio2, vi, rsvd4, 14, 30, 12 ),
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PG(dte, rsvd1, rsvd2, vi, spi1, 15, 31, 13 ),
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PG(dtf, i2c3, rsvd2, vi, rsvd4, 108, 110, 14 ),
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PG(gma, uarte, spi3, gmi, sdio4, 28, 16, 74 ),
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PG(gmb, ide, nand, gmi, gmi_int, 61, 46, 75 ),
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PG(gmc, uartd, spi4, gmi, sflash, 29, 17, 76 ),
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PG(gmd, rsvd1, nand, gmi, sflash, 62, 47, 77 ),
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PG(gme, rsvd1, dap5, gmi, sdio4, 32, 48, 44 ),
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PG(gpu, pwm, uarta, gmi, rsvd4, 16, 50, 26 ),
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PG(gpu7, rtck, rsvd2, rsvd3, rsvd4, 107, 109, 19 ),
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PG(gpv, pcie, rsvd2, rsvd3, rsvd4, 17, 49, 15 ),
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PG(hdint, hdmi, rsvd2, rsvd3, rsvd4, 87, 18, -1 ),
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PG(i2cp, i2cp, rsvd2, rsvd3, rsvd4, 18, 36, 17 ),
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PG(irrx, uarta, uartb, gmi, spi4, 20, 41, 43 ),
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PG(irtx, uarta, uartb, gmi, spi4, 19, 40, 42 ),
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PG(kbca, kbc, nand, sdio2, emc_test0_dll, 22, 37, 20 ),
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PG(kbcb, kbc, nand, sdio2, mio, 21, 38, 21 ),
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PG(kbcc, kbc, nand, trace, emc_test1_dll, 58, 39, 22 ),
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PG(kbcd, kbc, nand, sdio2, mio, 106, 108, 23 ),
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PG(kbce, kbc, nand, owr, rsvd4, 26, 14, 65 ),
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PG(kbcf, kbc, nand, trace, mio, 27, 13, 64 ),
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PG(lcsn, displaya, displayb, spi3, rsvd4, 95, 70, -1 ),
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PG(ld0, displaya, displayb, xio, rsvd4, 64, 80, -1 ),
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PG(ld1, displaya, displayb, xio, rsvd4, 65, 81, -1 ),
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PG(ld2, displaya, displayb, xio, rsvd4, 66, 82, -1 ),
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PG(ld3, displaya, displayb, xio, rsvd4, 67, 83, -1 ),
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PG(ld4, displaya, displayb, xio, rsvd4, 68, 84, -1 ),
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PG(ld5, displaya, displayb, xio, rsvd4, 69, 85, -1 ),
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PG(ld6, displaya, displayb, xio, rsvd4, 70, 86, -1 ),
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PG(ld7, displaya, displayb, xio, rsvd4, 71, 87, -1 ),
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PG(ld8, displaya, displayb, xio, rsvd4, 72, 88, -1 ),
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PG(ld9, displaya, displayb, xio, rsvd4, 73, 89, -1 ),
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PG(ld10, displaya, displayb, xio, rsvd4, 74, 90, -1 ),
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PG(ld11, displaya, displayb, xio, rsvd4, 75, 91, -1 ),
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PG(ld12, displaya, displayb, xio, rsvd4, 76, 92, -1 ),
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PG(ld13, displaya, displayb, xio, rsvd4, 77, 93, -1 ),
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PG(ld14, displaya, displayb, xio, rsvd4, 78, 94, -1 ),
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PG(ld15, displaya, displayb, xio, rsvd4, 79, 95, -1 ),
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PG(ld16, displaya, displayb, xio, rsvd4, 80, 96, -1 ),
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PG(ld17, displaya, displayb, rsvd3, rsvd4, 81, 97, -1 ),
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PG(ldc, displaya, displayb, rsvd3, rsvd4, 94, 71, -1 ),
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PG(ldi, displaya, displayb, rsvd3, rsvd4, 102, 104, -1 ),
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PG(lhp0, displaya, displayb, rsvd3, rsvd4, 82, 101, -1 ),
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PG(lhp1, displaya, displayb, rsvd3, rsvd4, 83, 98, -1 ),
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PG(lhp2, displaya, displayb, rsvd3, rsvd4, 84, 99, -1 ),
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PG(lhs, displaya, displayb, xio, rsvd4, 103, 75, -1 ),
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PG(lm0, displaya, displayb, spi3, rsvd4, 88, 77, -1 ),
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PG(lm1, displaya, displayb, rsvd3, CRT, 89, 78, -1 ),
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PG(lpp, displaya, displayb, rsvd3, rsvd4, 104, 103, -1 ),
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PG(lpw0, displaya, displayb, spi3, hdmi, 99, 64, -1 ),
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PG(lpw1, displaya, displayb, rsvd3, rsvd4, 100, 65, -1 ),
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PG(lpw2, displaya, displayb, spi3, hdmi, 101, 66, -1 ),
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PG(lsc0, displaya, displayb, xio, rsvd4, 91, 73, -1 ),
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PG(lsc1, displaya, displayb, spi3, hdmi, 92, 74, -1 ),
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PG(lsck, displaya, displayb, spi3, hdmi, 93, 72, -1 ),
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PG(lsda, displaya, displayb, spi3, hdmi, 97, 68, -1 ),
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PG(lsdi, displaya, displayb, spi3, rsvd4, 98, 67, -1 ),
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PG(lspi, displaya, displayb, xio, hdmi, 96, 69, -1 ),
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PG(lvp0, displaya, displayb, rsvd3, rsvd4, 85, 79, -1 ),
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PG(lvp1, displaya, displayb, rsvd3, rsvd4, 86, 100, -1 ),
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PG(lvs, displaya, displayb, xio, rsvd4, 90, 76, -1 ),
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PG(owc, owr, rsvd2, rsvd3, rsvd4, 31, 20, 79 ),
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PG(pmc, pwr_on, pwr_intr, rsvd3, rsvd4, 23, 105, -1 ),
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PG(pta, i2c2, hdmi, gmi, rsvd4, 24, 107, 18 ),
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PG(rm, i2c1, rsvd2, rsvd3, rsvd4, 25, 7, 16 ),
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PG(sdb, uarta, pwm, sdio3, spi2, 111, 53, -1 ),
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PG(sdc, pwm, twc, sdio3, spi3, 33, 54, 62 ),
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PG(sdd, uarta, pwm, sdio3, spi3, 34, 55, 63 ),
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PG(sdio1, sdio1, rsvd2, uarte, uarta, 30, 15, 73 ),
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PG(slxa, pcie, spi4, sdio3, spi2, 36, 19, 27 ),
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PG(slxc, spdif, spi4, sdio3, spi2, 37, 21, 29 ),
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PG(slxd, spdif, spi4, sdio3, spi2, 38, 22, 30 ),
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PG(slxk, pcie, spi4, sdio3, spi2, 39, 23, 31 ),
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PG(spdi, spdif, rsvd2, i2c1, sdio2, 40, 52, 24 ),
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PG(spdo, spdif, rsvd2, i2c1, sdio2, 41, 51, 25 ),
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PG(spia, spi1, spi2, spi3, gmi, 42, 63, 34 ),
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PG(spib, spi1, spi2, spi3, gmi, 43, 62, 35 ),
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PG(spic, spi1, spi2, spi3, gmi, 44, 61, 36 ),
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PG(spid, spi2, spi1, spi2_alt, gmi, 45, 60, 37 ),
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PG(spie, spi2, spi1, spi2_alt, gmi, 46, 59, 38 ),
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PG(spif, spi3, spi1, spi2, rsvd4, 47, 58, 39 ),
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PG(spig, spi3, spi2, spi2_alt, i2c1, 48, 57, 40 ),
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PG(spih, spi3, spi2, spi2_alt, i2c1, 49, 56, 41 ),
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PG(uaa, spi3, mipi_hs, uarta, ulpi, 50, 0, 48 ),
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PG(uab, spi2, mipi_hs, uarta, ulpi, 51, 1, 49 ),
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PG(uac, owr, rsvd2, rsvd3, rsvd4, 52, 2, 50 ),
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PG(uad, irda, spdif, uarta, spi4, 53, 3, 51 ),
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PG(uca, uartc, rsvd2, gmi, rsvd4, 54, 24, 52 ),
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PG(ucb, uartc, pwm, gmi, rsvd4, 55, 25, 53 ),
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PG(uda, spi1, rsvd2, uartd, ulpi, 109, 4, 72 ),
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};
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static void pinctrl_tegra20_set_func(struct pinctrl_tegra20 *ctrl,
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int muxctrl_id, int func)
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{
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u32 __iomem *regaddr = ctrl->regs.mux;
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u32 reg;
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int maskbit;
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regaddr += muxctrl_id >> 4;
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maskbit = (muxctrl_id << 1) & 0x1f;
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reg = readl(regaddr);
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reg &= ~(0x3 << maskbit);
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reg |= func << maskbit;
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writel(reg, regaddr);
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}
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static void pinctrl_tegra20_set_pull(struct pinctrl_tegra20 *ctrl,
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int pullctrl_id, int pull)
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{
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u32 __iomem *regaddr = ctrl->regs.pull;
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u32 reg;
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int maskbit;
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regaddr += pullctrl_id >> 4;
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maskbit = (pullctrl_id << 1) & 0x1f;
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reg = readl(regaddr);
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reg &= ~(0x3 << maskbit);
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reg |= pull << maskbit;
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writel(reg, regaddr);
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}
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static void pinctrl_tegra20_set_tristate(struct pinctrl_tegra20 *ctrl,
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int trictrl_id, int tristate)
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{
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u32 __iomem *regaddr = ctrl->regs.tri;
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u32 reg;
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int maskbit;
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regaddr += trictrl_id >> 5;
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maskbit = trictrl_id & 0x1f;
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reg = readl(regaddr);
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reg &= ~(1 << maskbit);
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reg |= tristate << maskbit;
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writel(reg, regaddr);
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}
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static int pinctrl_tegra20_set_state(struct pinctrl_device *pdev,
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struct device_node *np)
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{
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struct pinctrl_tegra20 *ctrl =
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container_of(pdev, struct pinctrl_tegra20, pinctrl);
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struct device_node *childnode;
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int pull = -1, tri = -1, i, j, k;
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const char *pins, *func = NULL;
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const struct tegra20_pingroup *group;
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/*
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* At first look if the node we are pointed at has children,
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* which we may want to visit.
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*/
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list_for_each_entry(childnode, &np->children, parent_list)
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pinctrl_tegra20_set_state(pdev, childnode);
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/* read relevant state from devicetree */
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of_property_read_string(np, "nvidia,function", &func);
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of_property_read_u32_array(np, "nvidia,pull", &pull, 1);
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of_property_read_u32_array(np, "nvidia,tristate", &tri, 1);
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/* iterate over all pingroups referenced in the dt node */
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for (i = 0; ; i++) {
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if (of_property_read_string_index(np, "nvidia,pins", i, &pins))
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break;
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for (j = 0; j < ARRAY_SIZE(tegra20_groups); j++) {
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if (!strcmp(pins, tegra20_groups[j].name)) {
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group = &tegra20_groups[j];
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break;
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}
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}
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/* if no matching pingroup is found bail out */
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if (j == ARRAY_SIZE(tegra20_groups)) {
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dev_warn(ctrl->pinctrl.dev,
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"invalid pingroup %s referenced in node %s\n",
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pins, np->name);
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continue;
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}
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if (func) {
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for (k = 0; k < 4; k++) {
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if (!strcmp(func, group->funcs[k]))
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break;
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}
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if (k < 4)
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pinctrl_tegra20_set_func(ctrl,
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group->muxctrl_id, k);
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else
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dev_warn(ctrl->pinctrl.dev,
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"invalid function %s for pingroup %s in node %s\n",
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func, group->name, np->name);
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}
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if (pull >= 0) {
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if (group->pullctrl_id >= 0)
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pinctrl_tegra20_set_pull(ctrl,
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group->pullctrl_id,
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pull);
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else
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dev_warn(ctrl->pinctrl.dev,
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"pingroup %s in node %s doesn't support pull configuration\n",
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group->name, np->name);
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}
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if (tri >= 0)
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pinctrl_tegra20_set_tristate(ctrl,
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group->trictrl_id, tri);
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}
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return 0;
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}
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static struct pinctrl_ops pinctrl_tegra20_ops = {
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.set_state = pinctrl_tegra20_set_state,
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};
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static int pinctrl_tegra20_probe(struct device_d *dev)
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{
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struct pinctrl_tegra20 *ctrl;
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int i, ret;
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u32 **regs;
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ctrl = xzalloc(sizeof(*ctrl));
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/*
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* Tegra pincontrol is split out into four independent memory ranges:
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* tristate control, function mux, pullup/down control, pad control
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* (from lowest to highest hardware address).
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* We are only interested in the first three for now.
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*/
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regs = (u32 **)&ctrl->regs;
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for (i = 0; i <= 2; i++) {
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regs[i] = dev_request_mem_region(dev, i);
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if (!regs[i]) {
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dev_err(dev, "Could not get iomem region %d\n", i);
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return -ENODEV;
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}
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}
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ctrl->pinctrl.dev = dev;
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ctrl->pinctrl.ops = &pinctrl_tegra20_ops;
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ret = pinctrl_register(&ctrl->pinctrl);
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if (ret)
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free(ctrl);
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return ret;
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}
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static __maybe_unused struct of_device_id pinctrl_tegra20_dt_ids[] = {
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{
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.compatible = "nvidia,tegra20-pinmux",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d pinctrl_tegra20_driver = {
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.name = "pinctrl-tegra20",
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.probe = pinctrl_tegra20_probe,
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.of_compatible = DRV_OF_COMPAT(pinctrl_tegra20_dt_ids),
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};
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static int pinctrl_tegra20_init(void)
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{
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return platform_driver_register(&pinctrl_tegra20_driver);
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}
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postcore_initcall(pinctrl_tegra20_init);
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