280 lines
7.2 KiB
C
280 lines
7.2 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* based on
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*
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* samsung/clk.c
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/clk.h>
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#include "clk.h"
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#include <init.h>
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/**
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* Register a clock branch.
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* Most clock branches have a form like
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*
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* src1 --|--\
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* |M |--[GATE]-[DIV]-
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* src2 --|--/
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*
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* sometimes without one of those components.
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*/
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static struct clk *rockchip_clk_register_branch(const char *name,
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const char **parent_names, u8 num_parents, void __iomem *base,
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int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
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u8 div_shift, u8 div_width, u8 div_flags,
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struct clk_div_table *div_table, int gate_offset,
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u8 gate_shift, u8 gate_flags, unsigned long flags
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)
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{
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struct clk *clk;
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struct clk *mux = NULL;
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struct clk *gate = NULL;
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struct clk *div = NULL;
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if (num_parents > 1) {
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mux = clk_mux_alloc(name, base + muxdiv_offset, mux_shift,
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mux_width, parent_names, num_parents, mux_flags);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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}
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if (gate_offset >= 0) {
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gate = clk_gate_alloc(name, *parent_names, base + gate_offset,
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gate_shift, flags, gate_flags);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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}
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if (div_width > 0) {
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div = clk_divider_alloc(name, *parent_names,
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base + muxdiv_offset, div_shift, div_width, div_flags);
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if (!div)
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return ERR_PTR(-ENOMEM);
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}
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clk = clk_register_composite(name, parent_names, num_parents,
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mux,
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div,
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gate,
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flags);
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return clk;
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}
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static struct clk *rockchip_clk_register_frac_branch(const char *name,
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const char **parent_names, u8 num_parents, void __iomem *base,
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int muxdiv_offset, u8 div_flags,
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int gate_offset, u8 gate_shift, u8 gate_flags,
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unsigned long flags)
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{
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struct clk *clk;
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struct clk *gate = NULL;
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struct clk *div = NULL;
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if (gate_offset >= 0) {
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gate = clk_gate_alloc(name, *parent_names, base + gate_offset,
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gate_shift, flags, gate_flags);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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}
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if (muxdiv_offset < 0)
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return ERR_PTR(-EINVAL);
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div = clk_fractional_divider_alloc(name, *parent_names, flags,
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base + muxdiv_offset, 16, 16, 0, 16, div_flags);
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if (!div)
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return ERR_PTR(-ENOMEM);
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clk = clk_register_composite(name, parent_names, num_parents,
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NULL,
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div,
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gate,
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flags);
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return clk;
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}
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static struct clk **clk_table;
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static void __iomem *reg_base;
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static struct clk_onecell_data clk_data;
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static struct device_node *cru_node;
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void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
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unsigned long nr_clks)
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{
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reg_base = base;
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cru_node = np;
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clk_table = calloc(nr_clks, sizeof(struct clk *));
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if (!clk_table)
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pr_err("%s: could not allocate clock lookup table\n", __func__);
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clk_data.clks = clk_table;
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clk_data.clk_num = nr_clks;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
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{
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if (clk_table && id)
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clk_table[id] = clk;
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}
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void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
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unsigned int nr_pll, int grf_lock_offset)
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{
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struct clk *clk;
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int idx;
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for (idx = 0; idx < nr_pll; idx++, list++) {
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clk = rockchip_clk_register_pll(list->type, list->name,
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list->parent_names, list->num_parents,
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reg_base, list->con_offset, grf_lock_offset,
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list->lock_shift, list->mode_offset,
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list->mode_shift, list->rate_table,
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list->pll_flags);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n", __func__,
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list->name);
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continue;
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}
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rockchip_clk_add_lookup(clk, list->id);
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}
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}
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void __init rockchip_clk_register_branches(
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struct rockchip_clk_branch *list,
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unsigned int nr_clk)
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{
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struct clk *clk = NULL;
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unsigned int idx;
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unsigned long flags;
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for (idx = 0; idx < nr_clk; idx++, list++) {
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flags = list->flags;
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/* catch simple muxes */
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switch (list->branch_type) {
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case branch_mux:
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/*
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* mux_flags and flags are ored, this is safe,
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* since there is no value clash, but isn't that elegant
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*/
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clk = clk_mux(list->name,
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reg_base + list->muxdiv_offset, list->mux_shift,
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list->mux_width, list->parent_names,
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list->num_parents, list->mux_flags | flags);
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break;
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case branch_divider:
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if (list->div_table)
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clk = clk_divider_table(list->name,
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list->parent_names[0],
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reg_base + list->muxdiv_offset,
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list->div_shift, list->div_width,
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list->div_table, list->div_flags);
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else
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clk = clk_divider(list->name,
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list->parent_names[0],
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reg_base + list->muxdiv_offset,
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list->div_shift, list->div_width,
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list->div_flags);
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break;
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case branch_fraction_divider:
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clk = rockchip_clk_register_frac_branch(list->name,
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list->parent_names, list->num_parents,
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reg_base, list->muxdiv_offset, list->div_flags,
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list->gate_offset, list->gate_shift,
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list->gate_flags, flags);
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break;
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case branch_gate:
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flags |= CLK_SET_RATE_PARENT;
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clk = clk_gate(list->name, list->parent_names[0],
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reg_base + list->gate_offset, list->gate_shift,
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flags, list->gate_flags);
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break;
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case branch_composite:
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clk = rockchip_clk_register_branch(list->name,
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list->parent_names, list->num_parents,
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reg_base, list->muxdiv_offset, list->mux_shift,
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list->mux_width, list->mux_flags,
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list->div_shift, list->div_width,
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list->div_flags, list->div_table,
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list->gate_offset, list->gate_shift,
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list->gate_flags, flags);
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break;
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case branch_mmc:
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break;
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}
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/* none of the cases above matched */
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if (!clk) {
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pr_err("%s: unknown clock type %d\n",
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__func__, list->branch_type);
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continue;
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}
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s: %ld\n",
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__func__, list->name, PTR_ERR(clk));
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continue;
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}
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rockchip_clk_add_lookup(clk, list->id);
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}
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}
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void __init rockchip_clk_register_armclk(unsigned int lookup_id,
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const char *name, const char **parent_names,
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u8 num_parents,
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const struct rockchip_cpuclk_reg_data *reg_data,
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const struct rockchip_cpuclk_rate_table *rates,
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int nrates)
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{
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struct clk *clk;
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clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents,
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reg_data, rates, nrates, reg_base
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);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s: %ld\n",
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__func__, name, PTR_ERR(clk));
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return;
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}
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rockchip_clk_add_lookup(clk, lookup_id);
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}
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void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks)
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{
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int i;
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/* Protect the clocks that needs to stay on */
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for (i = 0; i < nclocks; i++) {
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struct clk *clk = __clk_lookup(clocks[i]);
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if (clk)
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clk_enable(clk);
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}
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}
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