301 lines
7.0 KiB
C
301 lines
7.0 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <commproc.h>
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#include <net.h>
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#include <command.h>
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/**************************************************************
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*
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* FEC Ethernet Initialization Routine
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*
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*************************************************************/
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#define FEC_ECNTRL_ETHER_EN 0x00000002
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#define FEC_ECNTRL_RESET 0x00000001
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#define FEC_RCNTRL_BC_REJ 0x00000010
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#define FEC_RCNTRL_PROM 0x00000008
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#define FEC_RCNTRL_MII_MODE 0x00000004
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#define FEC_RCNTRL_DRT 0x00000002
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#define FEC_RCNTRL_LOOP 0x00000001
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#define FEC_TCNTRL_FDEN 0x00000004
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#define FEC_TCNTRL_HBC 0x00000002
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#define FEC_TCNTRL_GTS 0x00000001
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#define FEC_RESET_DELAY 50000
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define TOUT_LOOP 100
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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#define PKT_MAXBLR_SIZE 1520
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#ifdef CONFIG_M5272
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#define FEC_ADDR 0x10000840
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#endif
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#ifdef CONFIG_M5282
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#define FEC_ADDR 0x40001000
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#endif
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#undef ET_DEBUG
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#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
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static char txbuf[DBUF_LENGTH];
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* FEC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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typedef volatile struct CommonBufferDescriptor {
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cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
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cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
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} RTXBD;
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static RTXBD *rtx = 0x380000;
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int eth_send(volatile void *packet, int length)
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{
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int j, rc;
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volatile fec_t *fecp = FEC_ADDR;
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/* section 16.9.23.3
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* Wait for ready
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*/
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j = 0;
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while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j>=TOUT_LOOP) {
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printf("TX not ready\n");
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}
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rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
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rtx->txbd[txIdx].cbd_datlen = length;
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rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
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/* Activate transmit Buffer Descriptor polling */
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fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
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j = 0;
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while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
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udelay(1);
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j++;
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}
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if (j>=TOUT_LOOP) {
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printf("TX timeout\n");
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}
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#ifdef ET_DEBUG
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printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
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__FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
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(rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
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#endif
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/* return only status bits */;
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rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
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txIdx = (txIdx + 1) % TX_BUF_CNT;
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return rc;
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}
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int eth_rx(void)
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{
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int length;
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volatile fec_t *fecp = FEC_ADDR;
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for (;;)
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{
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/* section 16.9.23.2 */
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if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = rtx->rxbd[rxIdx].cbd_datlen;
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if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
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#ifdef ET_DEBUG
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printf("%s[%d] err: %x\n",
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__FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
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#endif
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} else {
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/* Pass the packet up to the protocol layers. */
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NetReceive(NetRxPackets[rxIdx], length - 4);
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}
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/* Give the buffer back to the FEC. */
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rtx->rxbd[rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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rxIdx = 0;
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} else {
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rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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rxIdx++;
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}
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/* Try to fill Buffer Descriptors */
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fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
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}
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return length;
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}
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int eth_init (bd_t * bd)
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{
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int i;
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volatile fec_t *fecp = FEC_ADDR;
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/* Whack a reset.
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* A delay is required between a reset of the FEC block and
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* initialization of other FEC registers because the reset takes
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* some time to complete. If you don't delay, subsequent writes
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* to FEC registers might get killed by the reset routine which is
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* still in progress.
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*/
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fecp->fec_ecntrl = FEC_ECNTRL_RESET;
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for (i = 0;
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(fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
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++i) {
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udelay (1);
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}
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if (i == FEC_RESET_DELAY) {
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printf ("FEC_RESET_DELAY timeout\n");
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return 0;
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}
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/* We use strictly polling mode only
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*/
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fecp->fec_imask = 0;
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/* Clear any pending interrupt */
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fecp->fec_ievent = 0xffffffff;
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/* Set station address */
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#define ea bd->bi_enetaddr
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fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
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(ea[2] << 8) | (ea[3] ) ;
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fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16 ) ;
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#undef ea
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/* Clear multicast address hash table
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*/
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fecp->fec_hash_table_high = 0;
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fecp->fec_hash_table_low = 0;
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/* Set maximum receive buffer size.
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*/
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fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
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/*
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* Setup Buffers and Buffer Desriptors
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*/
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rxIdx = 0;
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txIdx = 0;
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/*
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* Setup Receiver Buffer Descriptors (13.14.24.18)
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* Settings:
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* Empty, Wrap
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*/
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for (i = 0; i < PKTBUFSRX; i++) {
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rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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rtx->rxbd[i].cbd_datlen = 0; /* Reset */
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rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
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}
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/*
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* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
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* Settings:
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* Last, Tx CRC
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*/
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for (i = 0; i < TX_BUF_CNT; i++) {
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rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
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rtx->txbd[i].cbd_datlen = 0; /* Reset */
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rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
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}
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rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/* Set receive and transmit descriptor base
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*/
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fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
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fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
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/* Enable MII mode
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*/
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/* Half duplex mode */
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fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE<<16) | FEC_RCNTRL_MII_MODE;
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fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE<<16) | FEC_RCNTRL_MII_MODE;
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fecp->fec_x_cntrl = 0;
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fecp->fec_mii_speed = 0;
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/* Now enable the transmit and receive processing
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*/
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fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
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/* And last, try to fill Rx Buffer Descriptors */
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fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
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return 1;
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}
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void eth_halt(void)
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{
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volatile fec_t *fecp = FEC_ADDR;
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fecp->fec_ecntrl = 0;
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}
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#endif
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