---=== SPD EEPROM Information ===--- EEPROM Checksum of bytes 0-62 OK (0xDF) Total number of bytes in EEPROM 256 Fundamental Memory type DDR2 SDRAM SPD Revision 1.2 ---=== Memory Characteristics ===--- Maximum module speed 800 MHz (PC2-6400) Size 2048 MB Banks x Rows x Columns x Bits 8 x 14 x 10 x 64 Ranks 2 SDRAM Device Width 8 bits Module Height 30.0 mm Module Type SO-DIMM (67.6 mm) DRAM Package Planar Voltage Interface Level SSTL 1.8V Module Configuration Type No Parity Refresh Rate Reduced (7.8 us) - Self Refresh Supported Burst Lengths 4, 8 Supported CAS Latencies (tCL) 6T tCL-tRCD-tRP-tRAS 6-6-6-18 as DDR2-800 Minimum Cycle Time 2.5 ns at CAS 6 Maximum Access Time 0.40 ns at CAS 6 Maximum Cycle Time (tCK max) 8 ns ---=== Timing Parameters ===--- Address/Command Setup Time Before Clock (tIS) 0.17 ns Address/Command Hold Time After Clock (tIH) 0.25 ns Data Input Setup Time Before Strobe (tDS) 0.05 ns Data Input Hold Time After Strobe (tDH) 0.12 ns Minimum Row Precharge Delay (tRP) 15.00 ns Minimum Row Active to Row Active Delay (tRRD) 7.50 ns Minimum RAS# to CAS# Delay (tRCD) 15.00 ns Minimum RAS# Pulse Width (tRAS) 45.00 ns Write Recovery Time (tWR) 15.00 ns Minimum Write to Read CMD Delay (tWTR) 7.50 ns Minimum Read to Pre-charge CMD Delay (tRTP) 7.50 ns Minimum Active to Auto-refresh Delay (tRC) 60.00 ns Minimum Recovery Delay (tRFC) 127 ns Maximum DQS to DQ Skew (tDQSQ) 0.20 ns Maximum Read Data Hold Skew (tQHS) 0.30 ns ---=== Manufacturing Information ===--- Manufacturer JEDEC ID 7f 98 00 00 00 00 00 00 Manufacturing Location Code 0x05 Part Number Manufacturing Date 2014-W47 Assembly Serial Number 0x43266892 Signed-off-by: Alexander Smirnov <alllecs@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
253 lines
11 KiB
C
253 lines
11 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef _DDR_SPD_H_
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#define _DDR_SPD_H_
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/*
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* Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM",
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* SPD Revision 1.2
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*/
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struct ddr2_spd_eeprom_s {
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uint8_t info_size; /* 0 # bytes written into serial memory */
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uint8_t chip_size; /* 1 Total # bytes of SPD memory device */
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uint8_t mem_type; /* 2 Fundamental memory type */
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uint8_t nrow_addr; /* 3 # of Row Addresses on this assembly */
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uint8_t ncol_addr; /* 4 # of Column Addrs on this assembly */
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uint8_t mod_ranks; /* 5 Number of DIMM Ranks */
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uint8_t dataw; /* 6 Module Data Width */
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uint8_t res_7; /* 7 Reserved */
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uint8_t voltage; /* 8 Voltage intf std of this assembly */
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uint8_t clk_cycle; /* 9 SDRAM Cycle time @ CL=X */
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uint8_t clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */
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uint8_t config; /* 11 DIMM Configuration type */
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uint8_t refresh; /* 12 Refresh Rate/Type */
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uint8_t primw; /* 13 Primary SDRAM Width */
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uint8_t ecw; /* 14 Error Checking SDRAM width */
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uint8_t res_15; /* 15 Reserved */
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uint8_t burstl; /* 16 Burst Lengths Supported */
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uint8_t nbanks; /* 17 # of Banks on Each SDRAM Device */
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uint8_t cas_lat; /* 18 CAS# Latencies Supported */
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uint8_t mech_char; /* 19 DIMM Mechanical Characteristics */
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uint8_t dimm_type; /* 20 DIMM type information */
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uint8_t mod_attr; /* 21 SDRAM Module Attributes */
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uint8_t dev_attr; /* 22 SDRAM Device Attributes */
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uint8_t clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-1 */
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uint8_t clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
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uint8_t clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-2 */
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uint8_t clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
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uint8_t trp; /* 27 Min Row Precharge Time (tRP)*/
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uint8_t trrd; /* 28 Min Row Active to Row Active (tRRD) */
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uint8_t trcd; /* 29 Min RAS to CAS Delay (tRCD) */
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uint8_t tras; /* 30 Minimum RAS Pulse Width (tRAS) */
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uint8_t rank_dens; /* 31 Density of each rank on module */
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uint8_t ca_setup; /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
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uint8_t ca_hold; /* 33 Addr+Cmd Hold Time After Clk (tIH) */
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uint8_t data_setup; /* 34 Data Input Setup Time Before Strobe
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(tDS) */
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uint8_t data_hold; /* 35 Data Input Hold Time
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After Strobe (tDH) */
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uint8_t twr; /* 36 Write Recovery time tWR */
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uint8_t twtr; /* 37 Int write to read delay tWTR */
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uint8_t trtp; /* 38 Int read to precharge delay tRTP */
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uint8_t mem_probe; /* 39 Mem analysis probe characteristics */
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uint8_t trctrfc_ext; /* 40 Extensions to trc and trfc */
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uint8_t trc; /* 41 Min Active to Auto refresh time tRC */
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uint8_t trfc; /* 42 Min Auto to Active period tRFC */
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uint8_t tckmax; /* 43 Max device cycle time tCKmax */
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uint8_t tdqsq; /* 44 Max DQS to DQ skew (tDQSQ max) */
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uint8_t tqhs; /* 45 Max Read DataHold skew (tQHS) */
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uint8_t pll_relock; /* 46 PLL Relock time */
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uint8_t Tcasemax; /* 47 Tcasemax */
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uint8_t psiTAdram; /* 48 Thermal Resistance of DRAM Package
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from Top (Case) to Ambient
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(Psi T-A DRAM) */
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uint8_t dt0_mode; /* 49 DRAM Case Temperature Rise from
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Ambient due to Activate-Precharge/Mode
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Bits (DT0/Mode Bits) */
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uint8_t dt2n_dt2q; /* 50 DRAM Case Temperature Rise from
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Ambient due to Precharge/Quiet Standby
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(DT2N/DT2Q) */
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uint8_t dt2p; /* 51 DRAM Case Temperature Rise from
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Ambient due to Precharge Power-Down
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(DT2P) */
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uint8_t dt3n; /* 52 DRAM Case Temperature Rise from
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Ambient due to Active Standby (DT3N) */
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uint8_t dt3pfast; /* 53 DRAM Case Temperature Rise from
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Ambient due to Active Power-Down with
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Fast PDN Exit (DT3Pfast) */
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uint8_t dt3pslow; /* 54 DRAM Case Temperature Rise from
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Ambient due to Active Power-Down with
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Slow PDN Exit (DT3Pslow) */
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uint8_t dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from
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Ambient due to Page Open Burst
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Read/DT4R4W Mode Bit
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(DT4R/DT4R4W Mode Bit) */
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uint8_t dt5b; /* 56 DRAM Case Temperature Rise from
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Ambient due to Burst Refresh (DT5B) */
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uint8_t dt7; /* 57 DRAM Case Temperature Rise from
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Ambient due to Bank Interleave Reads
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with Auto-Precharge (DT7) */
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uint8_t psiTApll; /* 58 Thermal Resistance of PLL Package
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form Top (Case) to Ambient
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(Psi T-A PLL) */
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uint8_t psiTAreg; /* 59 Thermal Reisitance of Register
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Package from Top (Case) to Ambient
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(Psi T-A Register) */
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uint8_t dtpllactive; /* 60 PLL Case Temperature Rise from
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Ambient due to PLL Active
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(DT PLL Active) */
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uint8_t dtregact; /* 61 Register Case Temperature Rise from
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Ambient due to Register Active/Mode
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Bit (DT Register Active/Mode Bit) */
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uint8_t spd_rev; /* 62 SPD Data Revision Code */
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uint8_t cksum; /* 63 Checksum for bytes 0-62 */
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uint8_t mid[8]; /* 64 Mfr's JEDEC ID code per JEP-106 */
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uint8_t mloc; /* 72 Manufacturing Location */
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uint8_t mpart[18]; /* 73 Manufacturer's Part Number */
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uint8_t rev[2]; /* 91 Revision Code */
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uint8_t mdate[2]; /* 93 Manufacturing Date */
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uint8_t sernum[4]; /* 95 Assembly Serial Number */
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uint8_t mspec[27]; /* 99-127 Manufacturer Specific Data */
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};
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struct ddr3_spd_eeprom_s {
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/* General Section: Bytes 0-59 */
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uint8_t info_size_crc; /* 0 # bytes written into serial memory,
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CRC coverage */
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uint8_t spd_rev; /* 1 Total # bytes of SPD mem device */
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uint8_t mem_type; /* 2 Key Byte / Fundamental mem type */
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uint8_t module_type; /* 3 Key Byte / Module Type */
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uint8_t density_banks; /* 4 SDRAM Density and Banks */
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uint8_t addressing; /* 5 SDRAM Addressing */
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uint8_t module_vdd; /* 6 Module nominal voltage, VDD */
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uint8_t organization; /* 7 Module Organization */
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uint8_t bus_width; /* 8 Module Memory Bus Width */
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uint8_t ftb_div; /* 9 Fine Timebase (FTB)
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Dividend / Divisor */
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uint8_t mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */
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uint8_t mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */
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uint8_t tck_min; /* 12 SDRAM Minimum Cycle Time */
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uint8_t res_13; /* 13 Reserved */
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uint8_t caslat_lsb; /* 14 CAS Latencies Supported,
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Least Significant Byte */
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uint8_t caslat_msb; /* 15 CAS Latencies Supported,
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Most Significant Byte */
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uint8_t taa_min; /* 16 Min CAS Latency Time */
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uint8_t twr_min; /* 17 Min Write REcovery Time */
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uint8_t trcd_min; /* 18 Min RAS# to CAS# Delay Time */
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uint8_t trrd_min; /* 19 Min Row Active to
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Row Active Delay Time */
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uint8_t trp_min; /* 20 Min Row Precharge Delay Time */
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uint8_t tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */
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uint8_t tras_min_lsb; /* 22 Min Active to Precharge
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Delay Time */
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uint8_t trc_min_lsb; /* 23 Min Active to Active/Refresh
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Delay Time, LSB */
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uint8_t trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */
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uint8_t trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */
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uint8_t twtr_min; /* 26 Min Internal Write to
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Read Command Delay Time */
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uint8_t trtp_min; /* 27 Min Internal Read to Precharge
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Command Delay Time */
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uint8_t tfaw_msb; /* 28 Upper Nibble for tFAW */
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uint8_t tfaw_min; /* 29 Min Four Activate Window
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Delay Time*/
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uint8_t opt_features; /* 30 SDRAM Optional Features */
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uint8_t therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
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uint8_t therm_sensor; /* 32 Module Thermal Sensor */
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uint8_t device_type; /* 33 SDRAM device type */
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int8_t fine_tck_min; /* 34 Fine offset for tCKmin */
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int8_t fine_taa_min; /* 35 Fine offset for tAAmin */
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int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */
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int8_t fine_trp_min; /* 37 Fine offset for tRPmin */
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int8_t fine_trc_min; /* 38 Fine offset for tRCmin */
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uint8_t res_39_59[21]; /* 39-59 Reserved, General Section */
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/* Module-Specific Section: Bytes 60-116 */
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union {
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struct {
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/* 60 (Unbuffered) Module Nominal Height */
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uint8_t mod_height;
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/* 61 (Unbuffered) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 62 (Unbuffered) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 63 (Unbuffered) Address Mapping from
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Edge Connector to DRAM */
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uint8_t addr_mapping;
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/* 64-116 (Unbuffered) Reserved */
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uint8_t res_64_116[53];
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} unbuffered;
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struct {
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/* 60 (Registered) Module Nominal Height */
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uint8_t mod_height;
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/* 61 (Registered) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 62 (Registered) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 63 DIMM Module Attributes */
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uint8_t modu_attr;
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/* 64 RDIMM Thermal Heat Spreader Solution */
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uint8_t thermal;
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/* 65 Register Manufacturer ID Code, LSB */
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uint8_t reg_id_lo;
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/* 66 Register Manufacturer ID Code, MSB */
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uint8_t reg_id_hi;
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/* 67 Register Revision Number */
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uint8_t reg_rev;
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/* 68 Register Type */
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uint8_t reg_type;
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/* 69-76 RC1,3,5..15 (MS Nib.)/RC0,2,4..14 (LS Nib.) */
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uint8_t rcw[8];
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} registered;
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uint8_t uc[57]; /* 60-116 Module-Specific Section */
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} mod_section;
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/* Unique Module ID: Bytes 117-125 */
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uint8_t mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */
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uint8_t mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */
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uint8_t mloc; /* 119 Mfg Location */
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uint8_t mdate[2]; /* 120-121 Mfg Date */
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uint8_t sernum[4]; /* 122-125 Module Serial Number */
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/* CRC: Bytes 126-127 */
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uint8_t crc[2]; /* 126-127 SPD CRC */
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/* Other Manufacturer Fields and User Space: Bytes 128-255 */
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uint8_t mpart[18]; /* 128-145 Mfg's Module Part Number */
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uint8_t mrev[2]; /* 146-147 Module Revision Code */
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uint8_t dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */
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uint8_t dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */
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uint8_t msd[26]; /* 150-175 Mfg's Specific Data */
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uint8_t cust[80]; /* 176-255 Open for Customer Use */
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};
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extern void ddr_spd_print(uint8_t *record);
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extern uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd);
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extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd);
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/* * Byte 2 Fundamental Memory Types. */
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#define SPD_MEMTYPE_DDR2 (0x08)
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#define SPD_MEMTYPE_DDR3 (0x0B)
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/* DIMM Type for DDR2 SPD (according to v1.3) */
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#define DDR2_SPD_DIMMTYPE_RDIMM (0x01)
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#define DDR2_SPD_DIMMTYPE_UDIMM (0x02)
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#define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04)
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#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06)
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#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07)
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#define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08)
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#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10)
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#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20)
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/* Byte 3 Key Byte / Module Type for DDR3 SPD */
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#define DDR3_SPD_MODULETYPE_MASK (0x0F)
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#define DDR3_SPD_MODULETYPE_UDIMM (0x02)
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#endif /* _DDR_SPD_H_ */
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