Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
299 lines
9.9 KiB
C
299 lines
9.9 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/clock-manager.h>
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#include <mach/socfpga-regs.h>
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#include <mach/generic.h>
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static inline void cm_wait_for_lock(void __iomem *cm, uint32_t mask)
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{
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while ((readl(cm + CLKMGR_INTER_ADDRESS) & mask) != mask);
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}
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/* function to poll in the fsm busy bit */
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static inline void cm_wait4fsm(void __iomem *cm)
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{
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while (readl(cm + CLKMGR_STAT_ADDRESS) & 1);
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}
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/*
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* function to write the bypass register which requires a poll of the
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* busy bit
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*/
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static inline void cm_write_bypass(void __iomem *cm, uint32_t val)
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{
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writel(val, cm + CLKMGR_BYPASS_ADDRESS);
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cm_wait4fsm(cm);
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}
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/* function to write the ctrl register which requires a poll of the busy bit */
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static inline void cm_write_ctrl(void __iomem *cm, uint32_t val)
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{
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writel(val, cm + CLKMGR_CTRL_ADDRESS);
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cm_wait4fsm(cm);
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}
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/* function to write a clock register that has phase information */
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static inline void cm_write_with_phase(uint32_t value,
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void __iomem *reg, uint32_t mask)
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{
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/* poll until phase is zero */
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while (readl(reg) & mask);
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writel(value, reg);
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while (readl(reg) & mask);
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}
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/*
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* Setup clocks while making no assumptions of the
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* previous state of the clocks.
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*
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* - Start by being paranoid and gate all sw managed clocks
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* - Put all plls in bypass
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* - Put all plls VCO registers back to reset value (bgpwr dwn).
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* - Put peripheral and main pll src to reset value to avoid glitch.
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* - Delay 5 us.
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* - Deassert bg pwr dn and set numerator and denominator
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* - Start 7 us timer.
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* - set internal dividers
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* - Wait for 7 us timer.
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* - Enable plls
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* - Set external dividers while plls are locking
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* - Wait for pll lock
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* - Assert/deassert outreset all.
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* - Take all pll's out of bypass
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* - Clear safe mode
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* - set source main and peripheral clocks
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* - Ungate clocks
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*/
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void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg)
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{
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uint32_t mainvco, periphvco, val;
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void *cm = (void *)CYCLONE5_CLKMGR_ADDRESS;
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/* Start by being paranoid and gate all sw managed clocks */
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/*
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* We need to disable nandclk
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* and then do another apb access before disabling
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* gatting off the rest of the periperal clocks.
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*/
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val = readl(cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
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val &= ~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
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writel(val, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
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/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
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writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
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CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
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CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
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cm + CLKMGR_MAINPLLGRP_EN_ADDRESS);
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writel(0, cm + CLKMGR_SDRPLLGRP_EN_ADDRESS);
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/* now we can gate off the rest of the peripheral clocks */
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writel(0, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
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/* Put all plls in bypass */
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cm_write_bypass(cm,
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CLKMGR_BYPASS_PERPLL_SET(1) |
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CLKMGR_BYPASS_SDRPLL_SET(1) |
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CLKMGR_BYPASS_MAINPLL_SET(1));
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/*
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* Put all plls VCO registers back to reset value.
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* Some code might have messed with them.
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*/
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writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
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cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
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cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
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~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
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cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
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/*
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* The clocks to the flash devices and the L4_MAIN clocks can
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* glitch when coming out of safe mode if their source values
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* are different from their reset value. So the trick it to
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* put them back to their reset state, and change input
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* after exiting safe mode but before ungating the clocks.
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*/
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writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
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cm + CLKMGR_PERPLLGRP_SRC_ADDRESS);
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writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
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cm + CLKMGR_MAINPLLGRP_L4SRC_ADDRESS);
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/* read back for the required 5 us delay. */
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readl(cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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readl(cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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readl(cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
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/*
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* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
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* with numerator and denominator.
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*/
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writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN,
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cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN,
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cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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writel(cfg->sdram_vco_base |
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CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
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CLEAR_BGP_EN_PWRDN,
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cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
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writel(cfg->mpuclk, cm + CLKMGR_MAINPLLGRP_MPUCLK_ADDRESS);
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writel(cfg->mainclk, cm + CLKMGR_MAINPLLGRP_MAINCLK_ADDRESS);
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writel(cfg->alteragrp_mpu, cm + CLKMGR_ALTERAGRP_MPUCLK);
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writel(cfg->dbgatclk, cm + CLKMGR_MAINPLLGRP_DBGATCLK_ADDRESS);
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writel(cfg->alteregrp_main, cm + CLKMGR_ALTERAGRP_MAINCLK);
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writel(cfg->cfg2fuser0clk, cm + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_ADDRESS);
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writel(cfg->emac0clk, cm + CLKMGR_PERPLLGRP_EMAC0CLK_ADDRESS);
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writel(cfg->emac1clk, cm + CLKMGR_PERPLLGRP_EMAC1CLK_ADDRESS);
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writel(cfg->mainqspiclk, cm + CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS);
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writel(cfg->perqspiclk, cm + CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS);
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writel(cfg->mainnandsdmmcclk, cm + CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS);
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writel(cfg->pernandsdmmcclk, cm + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS);
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writel(cfg->perbaseclk, cm + CLKMGR_PERPLLGRP_PERBASECLK_ADDRESS);
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writel(cfg->s2fuser1clk, cm + CLKMGR_PERPLLGRP_S2FUSER1CLK_ADDRESS);
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/* 7 us must have elapsed before we can enable the VCO */
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__udelay(7);
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/* Enable vco */
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writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
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cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
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cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
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cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
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/* setup dividers while plls are locking */
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/* L3 MP and L3 SP */
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writel(cfg->maindiv, cm + CLKMGR_MAINPLLGRP_MAINDIV_ADDRESS);
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writel(cfg->dbgdiv, cm + CLKMGR_MAINPLLGRP_DBGDIV_ADDRESS);
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writel(cfg->tracediv, cm + CLKMGR_MAINPLLGRP_TRACEDIV_ADDRESS);
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/* L4 MP, L4 SP, can0, and can1 */
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writel(cfg->perdiv, cm + CLKMGR_PERPLLGRP_DIV_ADDRESS);
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writel(cfg->gpiodiv, cm + CLKMGR_PERPLLGRP_GPIODIV_ADDRESS);
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cm_wait_for_lock(cm, CLKMGR_INTER_SDRPLLLOCKED_MASK |
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CLKMGR_INTER_PERPLLLOCKED_MASK |
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CLKMGR_INTER_MAINPLLLOCKED_MASK);
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/* write the sdram clock counters before toggling outreset all */
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writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
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cm + CLKMGR_SDRPLLGRP_DDRDQSCLK_ADDRESS);
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writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
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cm + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_ADDRESS);
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writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
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cm + CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS);
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writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
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cm + CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS);
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/*
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* after locking, but before taking out of bypass
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* assert/deassert outresetall
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*/
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mainvco = readl(cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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/* assert main outresetall */
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writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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periphvco = readl(cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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/* assert pheriph outresetall */
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writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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/* assert sdram outresetall */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1) |
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CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
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cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
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/* deassert main outresetall */
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writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
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cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
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/* deassert pheriph outresetall */
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writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
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cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
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/* deassert sdram outresetall */
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
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cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
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/*
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* now that we've toggled outreset all, all the clocks
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* are aligned nicely; so we can change any phase.
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*/
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cm_write_with_phase(cfg->ddrdqsclk,
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cm + CLKMGR_SDRPLLGRP_DDRDQSCLK_ADDRESS,
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
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/* SDRAM DDR2XDQSCLK */
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cm_write_with_phase(cfg->ddr2xdqsclk,
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cm + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_ADDRESS,
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
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cm_write_with_phase(cfg->ddrdqclk,
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cm + CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS,
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
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cm_write_with_phase(cfg->s2fuser2clk,
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cm + CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS,
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
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/* Take all three PLLs out of bypass when safe mode is cleared. */
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cm_write_bypass(cm, 0);
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/* clear safe mode */
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val = readl(cm + CLKMGR_CTRL_ADDRESS);
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val |= CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK);
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cm_write_ctrl(cm, val);
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/*
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* now that safe mode is clear with clocks gated
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* it safe to change the source mux for the flashes the the L4_MAIN
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*/
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writel(cfg->persrc, cm + CLKMGR_PERPLLGRP_SRC_ADDRESS);
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writel(cfg->l4src, cm + CLKMGR_MAINPLLGRP_L4SRC_ADDRESS);
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/* Now ungate non-hw-managed clocks */
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writel(~0, cm + CLKMGR_MAINPLLGRP_EN_ADDRESS);
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writel(~0, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
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writel(~0, cm + CLKMGR_SDRPLLGRP_EN_ADDRESS);
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val = readl(cm + CLKMGR_DBCTRL_ADDRESS);
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val |= CLKMGR_DBCTRL_STAYOSC1_MASK;
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writel(val, cm + CLKMGR_DBCTRL_ADDRESS);
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}
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