105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
#include <common.h>
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#include <malloc.h>
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#include <envfs.h>
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#include <init.h>
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#include <io.h>
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#include <fs.h>
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/stat.h>
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#include <asm/memory.h>
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#include <mach/system-manager.h>
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#include <mach/reset-manager.h>
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#include <mach/socfpga-regs.h>
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#include <mach/nic301.h>
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#define SYSMGR_SDMMCGRP_CTRL_REG (CYCLONE5_SYSMGR_ADDRESS + 0x108)
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#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel) (((smplsel) & 0x7) << 3)
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#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel) ((drvsel) & 0x7)
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static int socfpga_detect_sdram(void)
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{
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void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
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uint32_t dramaddrw, ctrlwidth, memsize;
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int colbits, rowbits, bankbits;
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int width_bytes;
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dramaddrw = readl(base + 0x5000 + 0x2c);
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colbits = dramaddrw & 0x1f;
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rowbits = (dramaddrw >> 5) & 0x1f;
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bankbits = (dramaddrw >> 10) & 0x7;
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ctrlwidth = readl(base + 0x5000 + 0x60);
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switch (ctrlwidth & 0x3) {
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default:
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case 0:
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width_bytes = 1;
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break;
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case 1:
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width_bytes = 2;
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break;
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case 2:
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width_bytes = 4;
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break;
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}
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memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
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pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
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__func__, colbits, rowbits, bankbits, width_bytes, memsize);
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arm_add_mem_device("ram0", 0x0, memsize);
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return 0;
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}
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/* Some initialization for the EMAC */
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static void socfpga_init_emac(void)
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{
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uint32_t rst, val;
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/* No need for this without network support, e.g. xloader build */
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if (!IS_ENABLED(CONFIG_NET))
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return;
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/* According to Cyclone V datasheet, 17-60 "EMAC HPS Interface
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* Initialization", changing PHYSEL should be done with EMAC in reset
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* via permodrst. */
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/* Everything, except L4WD0/1, is out of reset via socfpga_lowlevel_init() */
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rst = readl(CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
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rst |= RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1;
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writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
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/* Set emac0/1 PHY interface select to RGMII. We could read phy-mode
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* from the device tree, if it was desired to support interfaces other
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* than RGMII. */
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val = readl(CONFIG_SYSMGR_EMAC_CTRL);
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val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB);
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val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB);
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val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
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val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
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writel(val, CONFIG_SYSMGR_EMAC_CTRL);
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/* Take emac0 and emac1 out of reset */
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rst &= ~(RSTMGR_PERMODRST_EMAC0 | RSTMGR_PERMODRST_EMAC1);
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writel(rst, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
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}
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static int socfpga_init(void)
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{
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socfpga_init_emac();
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writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0),
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SYSMGR_SDMMCGRP_CTRL_REG);
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nic301_slave_ns();
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socfpga_detect_sdram();
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return 0;
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}
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core_initcall(socfpga_init);
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