The current iocsr-config-cyclone5.c is actually board specific, although the file name suggests otherwise. As the file was generated for the SoCkit, move it there and add a new one for the socrates. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
59 lines
2 KiB
C
59 lines
2 KiB
C
#include <debug_ll.h>
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <mach/freeze-controller.h>
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#include <mach/system-manager.h>
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#include <mach/clock-manager.h>
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#include <mach/reset-manager.h>
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#include <mach/scan-manager.h>
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#include <mach/generic.h>
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void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
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struct socfpga_io_config *io_config)
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{
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uint32_t val;
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val = 0xffffffff;
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val &= ~(1 << RSTMGR_PERMODRST_L4WD0_LSB);
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val &= ~(1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
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writel(val, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
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/* freeze all IO banks */
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sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_0);
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sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_1);
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sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_2);
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sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_3);
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writel(~0, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_BRG_MOD_RESET_OFS);
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debug("Reconfigure Clock Manager\n");
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/* reconfigure the PLLs */
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socfpga_cm_basic_init(cm_config);
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debug("Configure IOCSR\n");
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/* configure the IOCSR through scan chain */
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scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_0, CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, io_config->iocsr_emac_mixed2);
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scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_1, CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, io_config->iocsr_mixed1_flash);
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scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_2, CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, io_config->iocsr_general);
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scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_3, CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, io_config->iocsr_ddr);
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/* configure the pin muxing through system manager */
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socfpga_sysmgr_pinmux_init(io_config->pinmux, io_config->num_pin);
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writel(RSTMGR_PERMODRST_L4WD0 | RSTMGR_PERMODRST_L4WD1,
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CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
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/* unfreeze / thaw all IO banks */
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sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_0);
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sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_1);
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sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_2);
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sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_3);
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writel(0x18, CYCLONE5_L3REGS_ADDRESS);
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writel(0x1, 0xfffefc00);
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INIT_LL();
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}
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