152 lines
3.5 KiB
C
152 lines
3.5 KiB
C
#include <platform_data/cadence_qspi.h>
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#include <platform_data/dw_mmc.h>
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#include <bootsource.h>
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#include <bootstrap.h>
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#include <platform_data/serial-ns16550.h>
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#include <common.h>
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#include <malloc.h>
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#include <init.h>
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#include <envfs.h>
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#include <linux/sizes.h>
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#include <fs.h>
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#include <io.h>
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#include <mci.h>
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#include <linux/clkdev.h>
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#include <linux/stat.h>
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#include <linux/clk.h>
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#include <mach/generic.h>
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#include <mach/system-manager.h>
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#include <mach/socfpga-regs.h>
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static struct socfpga_barebox_part default_part = {
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.nor_offset = SZ_256K,
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.nor_size = SZ_1M,
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.mmc_disk = "disk0.1",
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};
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const struct socfpga_barebox_part *barebox_part = &default_part;
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enum socfpga_clks {
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timer, mmc, qspi_clk, uart, clk_max
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};
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static struct clk *clks[clk_max];
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static struct dw_mmc_platform_data mmc_pdata = {
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.bus_width_caps = MMC_CAP_4_BIT_DATA,
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.ciu_div = 3,
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};
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static void socfpga_mmc_init(void)
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{
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clks[mmc] = clk_fixed("mmc", 400000000);
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clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL);
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add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K,
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IORESOURCE_MEM, &mmc_pdata);
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}
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#if defined(CONFIG_SPI_CADENCE_QUADSPI)
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static struct cadence_qspi_platform_data qspi_pdata = {
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.ext_decoder = 0,
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.fifo_depth = 128,
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};
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static __maybe_unused void add_cadence_qspi_device(int id, resource_size_t ctrl,
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resource_size_t data, void *pdata)
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{
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struct resource *res;
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res = xzalloc(sizeof(struct resource) * 2);
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res[0].start = ctrl;
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res[0].end = ctrl + 0x100 - 1;
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res[0].flags = IORESOURCE_MEM;
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res[1].start = data;
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res[1].end = data + 0x100 - 1;
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res[1].flags = IORESOURCE_MEM;
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add_generic_device_res("cadence_qspi", id, res, 2, pdata);
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}
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static __maybe_unused void socfpga_qspi_init(void)
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{
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clks[qspi_clk] = clk_fixed("qspi_clk", 370000000);
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clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_CTRL_ADDRESS, NULL);
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clkdev_add_physbase(clks[qspi_clk], CYCLONE5_QSPI_DATA_ADDRESS, NULL);
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add_cadence_qspi_device(0, CYCLONE5_QSPI_CTRL_ADDRESS,
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CYCLONE5_QSPI_DATA_ADDRESS, &qspi_pdata);
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}
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#else
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static void socfpga_qspi_init(void)
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{
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return;
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}
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#endif
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static struct NS16550_plat uart_pdata = {
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.clock = 100000000,
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.shift = 2,
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};
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static void socfpga_uart_init(void)
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{
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clks[uart] = clk_fixed("uart", 100000000);
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clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
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clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
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add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM |
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IORESOURCE_MEM_8BIT, &uart_pdata);
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}
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static void socfpga_timer_init(void)
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{
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clks[timer] = clk_fixed("timer", 200000000);
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clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
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add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100,
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IORESOURCE_MEM, NULL);
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}
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static __noreturn int socfpga_xload(void)
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{
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enum bootsource bootsource = bootsource_get();
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void *buf;
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switch (bootsource) {
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case BOOTSOURCE_MMC:
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socfpga_mmc_init();
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buf = bootstrap_read_disk(barebox_part->mmc_disk, "fat");
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break;
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case BOOTSOURCE_SPI:
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socfpga_qspi_init();
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buf = bootstrap_read_devfs("mtd0", false, barebox_part->nor_offset,
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barebox_part->nor_size, SZ_1M);
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break;
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default:
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pr_err("unknown bootsource %d\n", bootsource);
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hang();
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}
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if (!buf) {
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pr_err("failed to load barebox.bin\n");
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hang();
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}
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pr_info("starting bootloader...\n");
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bootstrap_boot(buf, 0);
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hang();
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}
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static int socfpga_devices_init(void)
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{
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barebox_set_model("SoCFPGA");
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socfpga_timer_init();
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socfpga_uart_init();
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barebox_main = socfpga_xload;
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return 0;
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}
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coredevice_initcall(socfpga_devices_init);
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