193 lines
3.9 KiB
C
193 lines
3.9 KiB
C
/*
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* bitops.h: Bit string operations on the ppc
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*/
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#ifndef _PPC_BITOPS_H
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#define _PPC_BITOPS_H
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#include <asm/byteorder.h>
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#include <asm-generic/bitops/ops.h>
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/*
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* Arguably these bit operations don't imply any memory barrier or
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* SMP ordering, but in fact a lot of drivers expect them to imply
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* both, since they do on x86 cpus.
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*/
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#ifdef CONFIG_SMP
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#define SMP_WMB "eieio\n"
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#define SMP_MB "\nsync"
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#else
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#define SMP_WMB
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#define SMP_MB
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#endif /* CONFIG_SMP */
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#define __INLINE_BITOPS 1
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#if __INLINE_BITOPS
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/*
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* These used to be if'd out here because using : "cc" as a constraint
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* resulted in errors from egcs. Things may be OK with gcc-2.95.
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*/
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static inline void set_bit(int nr, volatile void * addr)
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{
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unsigned long old;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\
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1: lwarx %0,0,%3\n\
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or %0,%0,%2\n\
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stwcx. %0,0,%3\n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc" );
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}
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static inline void clear_bit(int nr, volatile void *addr)
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{
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unsigned long old;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\
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1: lwarx %0,0,%3\n\
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andc %0,%0,%2\n\
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stwcx. %0,0,%3\n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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}
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static inline void change_bit(int nr, volatile void *addr)
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{
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unsigned long old;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\
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1: lwarx %0,0,%3\n\
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xor %0,%0,%2\n\
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stwcx. %0,0,%3\n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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}
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static inline int test_and_set_bit(int nr, volatile void *addr)
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{
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unsigned int old, t;
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unsigned int mask = 1 << (nr & 0x1f);
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volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\
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1: lwarx %0,0,%4\n\
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or %1,%0,%3\n\
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stwcx. %1,0,%4\n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=&r" (t), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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return (old & mask) != 0;
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}
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static inline int test_and_clear_bit(int nr, volatile void *addr)
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{
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unsigned int old, t;
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unsigned int mask = 1 << (nr & 0x1f);
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volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\
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1: lwarx %0,0,%4\n\
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andc %1,%0,%3\n\
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stwcx. %1,0,%4\n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=&r" (t), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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return (old & mask) != 0;
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}
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static inline int test_and_change_bit(int nr, volatile void *addr)
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{
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unsigned int old, t;
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unsigned int mask = 1 << (nr & 0x1f);
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volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
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__asm__ __volatile__(SMP_WMB "\
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1: lwarx %0,0,%4\n\
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xor %1,%0,%3\n\
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stwcx. %1,0,%4\n\
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bne 1b"
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SMP_MB
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: "=&r" (old), "=&r" (t), "=m" (*p)
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: "r" (mask), "r" (p), "m" (*p)
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: "cc");
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return (old & mask) != 0;
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}
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#endif /* __INLINE_BITOPS */
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/* Return the bit position of the most significant 1 bit in a word */
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static inline int __ilog2(unsigned int x)
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{
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int lz;
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asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
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return 31 - lz;
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}
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static inline int ffz(unsigned int x)
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{
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if ((x = ~x) == 0)
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return 32;
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return __ilog2(x & -x);
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}
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static inline int __ffs(unsigned long x)
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{
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return __ilog2(x & -x);
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}
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/*
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* fls: find last (most-significant) bit set.
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* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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*/
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static inline int fls(unsigned int x)
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{
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int lz;
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asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
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return 32 - lz;
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}
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#ifdef __KERNEL__
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/*
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* ffs: find first bit set. This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static inline int ffs(int x)
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{
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return __ilog2(x & -x) + 1;
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}
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/hweight.h>
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#endif /* __KERNEL__ */
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#include <asm-generic/bitops/find.h>
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#endif /* _PPC_BITOPS_H */
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