CPU, DDR, and LBC definitions are added to support the Freescale P1022. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
75 lines
2.5 KiB
C
75 lines
2.5 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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* Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __ASM_PPC_FSL_LBC_H
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#define __ASM_PPC_FSL_LBC_H
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#include <config.h>
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#include <common.h>
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/*
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* BR - Base Registers
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*/
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#define BR_PS 0x00001800
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#define BR_PS_SHIFT 11
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#define BR_PS_8 0x00000800 /* Port Size 8 bit */
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#define BR_PS_16 0x00001000 /* Port Size 16 bit */
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#define BR_PS_32 0x00001800 /* Port Size 32 bit */
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#define BR_DECC_SHIFT 9
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#define BR_V 0x00000001
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#define BR_V_SHIFT 0
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#define BR_MS_FCM 0x00000020
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#define BR_MS_UPMA 0x00000080
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/* Convert an address into the right format for the BR registers */
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#define BR_PHYS_ADDR(x) ((x) & 0xffff8000)
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/*
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* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
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* should always be zero on older parts that have a four bit CLKDIV.
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*/
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#define LCRR_CLKDIV 0x0000001f
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#define LCRR_CLKDIV_SHIFT 0
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#define LCRR_CLKDIV_4 0x00000002
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#define LCRR_CLKDIV_8 0x00000004
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#define LCRR_CLKDIV_16 0x00000008
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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/* LBC register offsets. */
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#define FSL_LBC_BRX(x) ((x) * 8) /* bank register offsets. */
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#define FSL_LBC_ORX(x) (4 + ((x) * 8)) /* option register offset. */
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#define FSL_LBC_LCCR 0x0d4 /* Clock ration register. */
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#define LBC_BASE_ADDR ((void __iomem *)LBC_ADDR)
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#define fsl_get_lbc_br(x) (in_be32((LBC_BASE_ADDR + FSL_LBC_BRX(x))))
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#define fsl_get_lbc_or(x) (in_be32((LBC_BASE_ADDR + FSL_LBC_ORX(x))))
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#define fsl_set_lbc_br(x, v) (out_be32((LBC_BASE_ADDR + FSL_LBC_BRX(x)), v))
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#define fsl_set_lbc_or(x, v) (out_be32((LBC_BASE_ADDR + FSL_LBC_ORX(x)), v))
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#define FSL_LBC_MAR_OFFSET 0x68
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#define FSL_LBC_MAMR_OFFSET 0x70
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#define FSL_LBC_MDR_OFFSET 0x88
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#define FSL_LBC_LTESR_OFFSET 0xB0
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#define FSL_LBC_LTEIR_OFFSET 0xB8
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#define FSL_LBC_LBCR_OFFSET 0xD0
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#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
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#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
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#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
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#define MxMR_OP_WARR 0x10000000 /* Write to Array */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PPC_FSL_LBC_H */
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