83b0a5ae05
This replaces the reset_cpu() function which every SoC or board must provide with registered handlers. This makes it possible to have multiple reset functions for boards which have multiple ways to reset the machine. Also boards which have no way at all to reset the machine no longer have to provide a dummy reset_cpu() function. The problem this solves is that some machines have external PMICs or similar to reset the system which have to be preferred over the internal SoC reset, because the PMIC can reset not only the SoC but also the external devices. To pick the right way to reset a machine each handler has a priority. The default priority is 100 and all currently existing restart handlers are registered with this priority. of_get_restart_priority() allows to retrieve the priority from the device tree which makes it possible for boards to give certain restart handlers a higher priority in order to use this one instead of the default one. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
103 lines
2.5 KiB
C
103 lines
2.5 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc
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* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <memory.h>
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#include <init.h>
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#include <restart.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm-generic/memory_layout.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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static void __noreturn mpc85xx_restart_soc(struct restart_handler *rst)
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{
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void __iomem *regs = (void __iomem *)MPC85xx_GUTS_ADDR;
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/* Everything after the first generation of PQ3 parts has RSTCR */
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out_be32(regs + MPC85xx_GUTS_RSTCR_OFFSET, 0x2); /* HRESET_REQ */
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udelay(100);
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hang();
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}
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static int restart_register_feature(void)
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{
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restart_handler_register_fn(mpc85xx_restart_soc);
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return 0;
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}
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coredevice_initcall(restart_register_feature);
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long int initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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if (IS_ENABLED(CONFIG_DDR_SPD))
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dram_size = fsl_ddr_sdram();
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else
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dram_size = fixed_sdram();
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dram_size = e500_setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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return dram_size;
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}
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/*
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* Return the memory size based on the configuration registers.
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*/
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phys_size_t fsl_get_effective_memsize(void)
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{
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void __iomem *regs = (void __iomem *)(MPC85xx_DDR_ADDR);
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phys_size_t sdram_size;
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uint san , ean;
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uint reg;
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int ix;
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sdram_size = 0;
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for (ix = 0; ix < CFG_CHIP_SELECTS_PER_CTRL; ix++) {
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if (in_be32(regs + DDR_OFF(CS0_CONFIG) + (ix * 4)) &
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SDRAM_CFG_MEM_EN) {
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reg = in_be32(regs + DDR_OFF(CS0_BNDS) + (ix * 8));
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/* start address */
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san = (reg & 0x0fff00000) >> 16;
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/* end address */
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ean = (reg & 0x00000fff);
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sdram_size += ((ean - san + 1) << 24);
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}
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}
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return sdram_size;
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}
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static int fsl_reserve_region(void)
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{
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request_sdram_region("stack", _text_base - STACK_SIZE,
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STACK_SIZE);
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return 0;
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}
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coredevice_initcall(fsl_reserve_region);
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