Add support for the Freescale P1010 including errata for this CPU, SoC frequency calculation and GPIO settings. The mpc85xx configuration options file is re-ordered to facilitate board option selection. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
219 lines
5.8 KiB
C
219 lines
5.8 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ifc.h>
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#include <mach/mpc85xx.h>
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#include <mach/mmu.h>
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#include <mach/immap_85xx.h>
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/* NOR workaround for P1010 erratum A003399 */
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#if defined(CONFIG_FSL_ERRATUM_P1010_A003549)
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#define SRAM_BASE_ADDR 0x100
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void setup_ifc(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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phys_addr_t flash_phys = CFG_FLASH_BASE_PHYS;
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/*
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* Adjust the TLB we were running out of to match the phys addr of the
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* chip select we are adjusting and will return to.
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*/
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flash_phys += (~CFG_IFC_AMASK0) + 1 - 4*1024*1024;
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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mas2 = FSL_BOOKE_MAS2(CONFIG_TEXT_BASE, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, mas0);
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mtspr(MAS1, mas1);
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mtspr(MAS2, mas2);
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mtspr(MAS3, mas3);
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mtspr(MAS7, mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#if defined(PPC_E500_DEBUG_TLB)
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/*
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* TLB entry for debuggging in AS1
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* Create temporary TLB entry in AS0 to handle debug exception
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* As on debug exception MSR is cleared i.e. Address space is
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* changed to 0. A TLB entry (in AS0) is required to handle
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* debug exception generated * in AS1.
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*
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* TLB entry is created for IVPR + IVOR15 to map on valid OP
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* code address because flash's physical address is going to
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* change as CFG_FLASH_BASE_PHYS.
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*/
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(PPC_E500_DEBUG_TLB);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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mas2 = FSL_BOOKE_MAS2(CONFIG_TEXT_BASE, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, mas0);
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mtspr(MAS1, mas1);
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mtspr(MAS2, mas2);
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mtspr(MAS3, mas3);
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mtspr(MAS7, mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#endif
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set_ifc_cspr(0, CFG_IFC_CSPR0);
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set_ifc_csor(0, CFG_IFC_CSOR0);
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set_ifc_amask(0, CFG_IFC_AMASK0);
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}
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void fsl_erratum_ifc_a003399(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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void __iomem *l2cache = IOMEM(MPC85xx_L2_ADDR);
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void (*setup_ifc_sram)(void) = (void *)SRAM_BASE_ADDR;
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u32 *dst, *src, ix;
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/* TLB for SRAM */
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
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MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
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mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0,
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MAS3_SX | MAS3_SW | MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(0);
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e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
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out_be32(l2cache + MPC85xx_L2_L2SRBAR0_OFFSET, SRAM_BASE_ADDR);
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out_be32(l2cache + MPC85xx_L2_L2ERRDIS_OFFSET,
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(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
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out_be32(l2cache + MPC85xx_L2_CTL_OFFSET,
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
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/*
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* Copy the code in setup_ifc to L2SRAM. Do a word copy
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* because NOR Flash on P1010 does not support byte
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* access (Erratum IFC-A002769)
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*/
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dst = (u32 *) SRAM_BASE_ADDR;
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src = (u32 *) setup_ifc;
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for (ix = 0; ix < 1024; ix++)
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*dst++ = *src++;
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setup_ifc_sram();
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clrbits_be32(l2cache + MPC85xx_L2_CTL_OFFSET,
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
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out_be32(l2cache + MPC85xx_L2_L2SRBAR0_OFFSET, 0x0);
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}
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#else
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void fsl_erratum_ifc_a003399(void) {}
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#endif
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int fsl_l2_cache_init(void)
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{
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void __iomem *l2cache = (void __iomem *)MPC85xx_L2_ADDR;
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uint cache_ctl;
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uint svr, ver;
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u32 l2siz_field;
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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asm("msync;isync");
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cache_ctl = in_be32(l2cache + MPC85xx_L2_CTL_OFFSET);
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l2siz_field = (cache_ctl >> 28) & 0x3;
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switch (l2siz_field) {
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case 0x0:
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return -1;
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break;
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case 0x1:
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cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, L2SRAM=0 */
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break;
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case 0x2:
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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case 0x3:
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/* set L2E=1, L2I=1, & L2SRAM=0 */
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cache_ctl = 0xc0000000;
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break;
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}
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if (!(in_be32(l2cache + MPC85xx_L2_CTL_OFFSET) & MPC85xx_L2CTL_L2E)) {
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asm("msync;isync");
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/* invalidate & enable */
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out_be32(l2cache + MPC85xx_L2_CTL_OFFSET, cache_ctl);
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asm("msync;isync");
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}
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return 0;
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}
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#if defined(CONFIG_FSL_ERRATUM_P1010_A003549)
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void fsl_erratum_p1010_a003549(void)
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{
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void __iomem *guts = IOMEM(MPC85xx_GUTS_ADDR);
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setbits_be32(guts + MPC85xx_GUTS_PMUXCR_OFFSET,
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MPC85xx_PMUXCR_LCLK_IFC_CS3);
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}
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#else
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void fsl_erratum_p1010_a003549(void) {}
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#endif
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void cpu_init_early_f(void)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
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MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(CFG_CCSRBAR, MAS2_I | MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CFG_CCSRBAR_PHYS, 0, MAS3_SW | MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CFG_CCSRBAR_PHYS);
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e500_write_tlb(mas0, mas1, mas2, mas3, mas7);
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fsl_erratum_p1010_a003549();
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fsl_init_laws();
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fsl_erratum_ifc_a003399();
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e500_invalidate_tlb(1);
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e500_init_tlbs();
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}
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static int cpu_init_r(void)
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{
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e500_disable_tlb(14);
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e500_disable_tlb(15);
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return 0;
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}
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core_initcall(cpu_init_r);
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