Removed the ppc bit operation functions and definitions in the ppc file asm/bitops.h since these are already defined in the asm-generic header files. Moved ffs64 definition to the mpc85xx header files because the function requires the inclusion of linux/log2.h which also includes asm/bitops.h. The conflict was noted when UBIFS was enabled in barebox. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
158 lines
3.6 KiB
C
158 lines
3.6 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/config.h>
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#include <asm/fsl_law.h>
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#include <mach/ffs64.h>
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#define FSL_HW_NUM_LAWS FSL_NUM_LAWS
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#define LAW_BASE (CFG_IMMR + 0xc08)
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#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * (x) + 2)
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#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * (x))
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#define LAWBAR_SHIFT 12
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static inline phys_addr_t fsl_get_law_base_addr(int idx)
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{
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return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
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}
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static inline void fsl_set_law_base_addr(int idx, phys_addr_t addr)
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{
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out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
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}
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static void fsl_set_law(u8 idx, phys_addr_t addr, enum law_size sz,
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enum law_trgt_if id)
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{
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out_be32(LAWAR_ADDR(idx), 0);
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fsl_set_law_base_addr(idx, addr);
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out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
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/* Read back so that we sync the writes */
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in_be32(LAWAR_ADDR(idx));
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}
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static int fsl_is_free_law(int idx)
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{
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u32 lawar;
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lawar = in_be32(LAWAR_ADDR(idx));
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if (!(lawar & LAW_EN))
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return 1;
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return 0;
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}
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static void fsl_set_next_law(phys_addr_t addr, enum law_size sz,
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enum law_trgt_if id)
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{
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u32 idx;
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for (idx = 0; idx < FSL_HW_NUM_LAWS; idx++) {
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if (fsl_is_free_law(idx)) {
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fsl_set_law(idx, addr, sz, id);
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break;
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}
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}
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if (idx >= FSL_HW_NUM_LAWS)
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panic("No more LAWS available\n");
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}
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static void fsl_set_last_law(phys_addr_t addr, enum law_size sz,
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enum law_trgt_if id)
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{
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u32 idx;
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for (idx = (FSL_HW_NUM_LAWS - 1); idx >= 0; idx--) {
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if (fsl_is_free_law(idx)) {
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fsl_set_law(idx, addr, sz, id);
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break;
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}
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}
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if (idx < 0)
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panic("No more LAWS available\n");
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}
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/* use up to 2 LAWs for DDR, use the last available LAWs */
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int fsl_set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
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{
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u64 start_align, law_sz;
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int law_sz_enc;
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if (start == 0)
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start_align = 1ull << (LAW_SIZE_32G + 1);
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else
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start_align = 1ull << (ffs64(start) - 1);
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law_sz = min(start_align, sz);
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law_sz_enc = __ilog2_u64(law_sz) - 1;
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fsl_set_last_law(start, law_sz_enc, id);
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/* recalculate size based on what was actually covered by the law */
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law_sz = 1ull << __ilog2_u64(law_sz);
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/* do we still have anything to map */
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sz = sz - law_sz;
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if (sz) {
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start += law_sz;
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start_align = 1ull << (ffs64(start) - 1);
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law_sz = min(start_align, sz);
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law_sz_enc = __ilog2_u64(law_sz) - 1;
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fsl_set_last_law(start, law_sz_enc, id);
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} else {
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return 0;
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}
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/* do we still have anything to map */
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sz = sz - law_sz;
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if (sz)
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return 1;
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return 0;
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}
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void fsl_init_laws(void)
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{
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int i;
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if (FSL_HW_NUM_LAWS > 32)
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panic("FSL_HW_NUM_LAWS can not be > 32 w/o code changes");
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for (i = 0; i < num_law_entries; i++) {
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if (law_table[i].index == -1)
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fsl_set_next_law(law_table[i].addr,
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law_table[i].size,
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law_table[i].trgt_id);
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else
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fsl_set_law(law_table[i].index, law_table[i].addr,
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law_table[i].size, law_table[i].trgt_id);
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}
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}
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