301 lines
8.7 KiB
C
301 lines
8.7 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <init.h>
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#include <common.h>
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#include <io.h>
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#include <linux/sizes.h>
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#include <mfd/imx6q-iomuxc-gpr.h>
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#include <mach/imx6.h>
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#include <mach/generic.h>
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#include <mach/revision.h>
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#include <mach/imx6-anadig.h>
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#include <mach/imx6-regs.h>
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#include <mach/generic.h>
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#include <asm/mmu.h>
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#include <asm/cache-l2x0.h>
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#define SI_REV 0x260
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void imx6_init_lowlevel(void)
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{
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void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
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void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
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void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
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bool is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
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bool is_imx6d = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6D;
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uint32_t val;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, aips1);
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writel(0x77777777, aips1 + 0x4);
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writel(0, aips1 + 0x40);
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writel(0, aips1 + 0x44);
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writel(0, aips1 + 0x48);
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writel(0, aips1 + 0x4c);
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writel(0, aips1 + 0x50);
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writel(0x77777777, aips2);
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writel(0x77777777, aips2 + 0x4);
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writel(0, aips2 + 0x40);
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writel(0, aips2 + 0x44);
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writel(0, aips2 + 0x48);
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writel(0, aips2 + 0x4c);
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writel(0, aips2 + 0x50);
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/* enable all clocks */
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writel(0xffffffff, 0x020c4068);
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writel(0xffffffff, 0x020c406c);
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writel(0xffffffff, 0x020c4070);
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writel(0xffffffff, 0x020c4074);
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writel(0xffffffff, 0x020c4078);
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writel(0xffffffff, 0x020c407c);
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writel(0xffffffff, 0x020c4080);
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/*
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* Due to a hardware bug (related to errata ERR006282) on i.MX6DQ we
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* need to gate/ungate all PFDs to make sure PFD is working right,
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* otherwise PFDs may not output clock after reset.
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*/
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if (is_imx6q || is_imx6d) {
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writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
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BM_ANADIG_PFD_480_PFD2_CLKGATE |
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BM_ANADIG_PFD_480_PFD1_CLKGATE |
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BM_ANADIG_PFD_480_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
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writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
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BM_ANADIG_PFD_528_PFD2_CLKGATE |
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BM_ANADIG_PFD_528_PFD1_CLKGATE |
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BM_ANADIG_PFD_528_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
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writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
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BM_ANADIG_PFD_480_PFD2_CLKGATE |
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BM_ANADIG_PFD_480_PFD1_CLKGATE |
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BM_ANADIG_PFD_480_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
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writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
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BM_ANADIG_PFD_528_PFD2_CLKGATE |
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BM_ANADIG_PFD_528_PFD1_CLKGATE |
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BM_ANADIG_PFD_528_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
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}
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val = readl(iomux + IOMUXC_GPR4);
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val |= IMX6Q_GPR4_VPU_WR_CACHE_SEL | IMX6Q_GPR4_VPU_RD_CACHE_SEL |
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IMX6Q_GPR4_VPU_P_WR_CACHE_VAL | IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
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IMX6Q_GPR4_IPU_WR_CACHE_CTL | IMX6Q_GPR4_IPU_RD_CACHE_CTL;
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writel(val, iomux + IOMUXC_GPR4);
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/* Increase IPU read QoS priority */
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val = readl(iomux + IOMUXC_GPR6);
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val &= ~(IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK | IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK);
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val |= (0xf << 16) | (0x7 << 20);
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writel(val, iomux + IOMUXC_GPR6);
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val = readl(iomux + IOMUXC_GPR7);
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val &= ~(IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK | IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK);
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val |= (0xf << 16) | (0x7 << 20);
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writel(val, iomux + IOMUXC_GPR7);
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}
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int imx6_init(void)
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{
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const char *cputypestr;
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u32 rev;
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u32 mx6_silicon_revision;
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imx6_init_lowlevel();
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imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
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rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
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switch (rev & 0xfff) {
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case 0x00:
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mx6_silicon_revision = IMX_CHIP_REV_1_0;
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break;
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case 0x01:
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mx6_silicon_revision = IMX_CHIP_REV_1_1;
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break;
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case 0x02:
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mx6_silicon_revision = IMX_CHIP_REV_1_2;
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break;
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case 0x03:
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mx6_silicon_revision = IMX_CHIP_REV_1_3;
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break;
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case 0x04:
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mx6_silicon_revision = IMX_CHIP_REV_1_4;
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break;
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case 0x05:
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mx6_silicon_revision = IMX_CHIP_REV_1_5;
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break;
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case 0x100:
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mx6_silicon_revision = IMX_CHIP_REV_2_0;
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break;
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default:
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mx6_silicon_revision = IMX_CHIP_REV_UNKNOWN;
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}
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switch (imx6_cpu_type()) {
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case IMX6_CPUTYPE_IMX6Q:
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if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
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cputypestr = "i.MX6 Quad Plus";
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else
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cputypestr = "i.MX6 Quad";
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break;
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case IMX6_CPUTYPE_IMX6D:
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if (mx6_silicon_revision >= IMX_CHIP_REV_2_0)
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cputypestr = "i.MX6 Dual Plus";
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else
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cputypestr = "i.MX6 Dual";
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break;
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case IMX6_CPUTYPE_IMX6DL:
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cputypestr = "i.MX6 DualLite";
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break;
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case IMX6_CPUTYPE_IMX6S:
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cputypestr = "i.MX6 Solo";
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break;
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case IMX6_CPUTYPE_IMX6SX:
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cputypestr = "i.MX6 SoloX";
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break;
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default:
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cputypestr = "unknown i.MX6";
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break;
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}
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imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
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return 0;
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}
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int imx6_devices_init(void)
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{
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add_generic_device("imx-iomuxv3", 0, NULL, MX6_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, MX6_GPT_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 2, NULL, MX6_GPIO3_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 3, NULL, MX6_GPIO4_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx21-wdt", 0, NULL, MX6_WDOG1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx6-usb-misc", 0, NULL, MX6_USBOH3_USB_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL);
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return 0;
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}
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static int imx6_mmu_init(void)
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{
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void __iomem *l2x0_base = IOMEM(0x00a02000);
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u32 val, cache_part, cache_rtl;
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if (!cpu_is_mx6())
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return 0;
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val = readl(l2x0_base + L2X0_CACHE_ID);
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cache_part = val & L2X0_CACHE_ID_PART_MASK;
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cache_rtl = val & L2X0_CACHE_ID_RTL_MASK;
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/* configure the PREFETCH register */
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val = readl(l2x0_base + L2X0_PREFETCH_CTRL);
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val |= L2X0_DOUBLE_LINEFILL_EN |
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L2X0_INSTRUCTION_PREFETCH_EN |
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L2X0_DATA_PREFETCH_EN;
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/*
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* set prefetch offset to 15
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*/
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val |= 15;
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/*
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* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
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* But according to ARM PL310 errata: 752271
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* ID: 752271: Double linefill feature can cause data corruption
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* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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* Workaround: The only workaround to this erratum is to disable the
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* double linefill feature. This is the default behavior.
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*/
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if (cache_part == L2X0_CACHE_ID_PART_L310 &&
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cache_rtl < L2X0_CACHE_ID_RTL_R3P2)
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val &= ~L2X0_DOUBLE_LINEFILL_EN;
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writel(val, l2x0_base + L2X0_PREFETCH_CTRL);
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/*
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* Set shared attribute override bit in AUX_CTRL register, this is done
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* here as it must be done regardless of the usage of the L2 cache in
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* barebox itself. The kernel will not touch this bit, but it must be
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* set to make the system compliant to the ARMv7 ARM RevC clarifications
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* regarding conflicting memory aliases.
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*/
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val = readl(l2x0_base + L2X0_AUX_CTRL);
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val |= (1 << 22);
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writel(val, l2x0_base + L2X0_AUX_CTRL);
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l2x0_init(l2x0_base, 0x0, ~0UL);
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return 0;
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}
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postmmu_initcall(imx6_mmu_init);
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#define SCU_CONFIG 0x04
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static int imx6_fixup_cpus(struct device_node *root, void *context)
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{
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struct device_node *cpus_node, *np, *tmp;
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unsigned long scu_phys_base;
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unsigned int max_core_index;
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cpus_node = of_find_node_by_name(root, "cpus");
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if (!cpus_node)
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return 0;
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/* get actual number of available CPU cores from SCU */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_phys_base));
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max_core_index = (readl(IOMEM(scu_phys_base) + SCU_CONFIG) & 0x03);
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for_each_child_of_node_safe(cpus_node, tmp, np) {
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u32 cpu_index;
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if (of_property_read_u32(np, "reg", &cpu_index))
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continue;
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if (cpu_index > max_core_index)
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of_delete_node(np);
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}
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return 0;
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}
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static int imx6_fixup_cpus_register(void)
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{
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if (!of_machine_is_compatible("fsl,imx6q") &&
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!of_machine_is_compatible("fsl,imx6dl"))
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return 0;
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return of_register_fixup(imx6_fixup_cpus, NULL);
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}
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device_initcall(imx6_fixup_cpus_register);
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