135 lines
4.6 KiB
C
135 lines
4.6 KiB
C
/*
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* (C) Copyright 2007 Pengutronix
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* Sascha Hauer, <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* ARM asynchronous clock */
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#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
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#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
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/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
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#define AT91_SLOW_CLOCK 32768 /* slow clock */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define USE_920T_MMU 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CFG_USE_MAIN_OSCILLATOR 1
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/* flash */
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#define MC_PUIA_VAL 0x00000000
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#define MC_PUP_VAL 0x00000000
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#define MC_PUER_VAL 0x00000000
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#define MC_ASR_VAL 0x00000000
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR_VAL 0x00000000
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#define SMC2_CSR_VAL 0x00003287
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/* clocks */
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#define PLLAR_VAL 0x2026be04
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#define PLLBR_VAL 0x10483e0e
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#define MCKR_VAL 0x00000202
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/* sdram */
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#define PIOC_ASR_VAL 0xffff0000
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#define PIOC_BSR_VAL 0x00000000
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#define PIOC_PDR_VAL 0xffff0000
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#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
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#define SDRAM 0x20000000 /* address of the SDRAM */
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#define SDRAM1 0x20000080 /* address of the SDRAM */
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#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define SDRC_MR_VAL1 0x00000004 /* refresh */
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#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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#define CONFIG_BAUDRATE 115200
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/*
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* Hardware drivers
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*/
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/* define one of CONFIG_DBGU, CONFIG_USART0 or CONFIG_USART1 to choose console */
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#define CONFIG_DBGU
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"mtdids=nor0=physmap-flash.0\0" \
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"mtdparts=mtdparts=physmap-flash.0:128k(uboot)ro,128k(env),1536k(kernel),-(jffs2)\0" \
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"bootargs_base=setenv bootargs console=ttyAT0,115200\0" \
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"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
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"bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock3 rootfstype=jffs2\0" \
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"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x11040000\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x20000000 $(uimage); bootm\0" \
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"autoload=n\0" \
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"uimage=uImage-eco920\0" \
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"jffs2=root-eco920.jffs2\0"
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x2000000
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#define CFG_MEMTEST_START PHYS_SDRAM
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#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
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#define CONFIG_DRIVER_ETHER
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91C_USE_RMII
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#define CFG_LOAD_ADDR 0x21000000 /* default load address */
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#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CFG_MAXARGS 32 /* max number of command args */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CLOCK_TICK_RATE AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
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/* AT91C_TC_TIMER_DIV1_CLOCK */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
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#define CFG_SPLASH 1
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#define CFG_S1D13706FB 1
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#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
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#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
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#define LITTLEENDIAN
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#define CONFIG_AT91C_PQFP_UHPBUG
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#endif
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