This moves the CCM drivers to core_initcall since this has no dependencies. This way we can be sure that the clock for the clocksource is available in at postcore_initcall time. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
118 lines
3.5 KiB
C
118 lines
3.5 KiB
C
/*
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* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/imx1-regs.h>
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#include "clk.h"
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#define CCM_CSCR 0x0
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#define CCM_MPCTL0 0x4
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#define CCM_SPCTL0 0xc
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#define CCM_PCDR 0x20
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enum imx1_clks {
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dummy, clk32, clk16m, clk32_premult, prem, mpll, spll, mcu,
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fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
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mma_gate, usbd_gate, clk_max
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};
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static struct clk *clks[clk_max];
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static const char *prem_sel_clks[] = {
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"clk32_premult",
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"clk16m",
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};
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static const char *clko_sel_clks[] = {
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"per1",
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"hclk",
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"clk48m",
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"clk16m",
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"prem",
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"fclk",
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};
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int __init mx1_clocks_init(void __iomem *regs, unsigned long fref)
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{
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clks[dummy] = clk_fixed("dummy", 0);
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clks[clk32] = clk_fixed("clk32", fref);
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clks[clk16m] = clk_fixed("clk16m", 16000000);
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clks[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
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clks[prem] = imx_clk_mux("prem", regs + CCM_CSCR, 16, 1, prem_sel_clks,
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ARRAY_SIZE(prem_sel_clks));
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clks[mpll] = imx_clk_pllv1("mpll", "clk32_premult", regs + CCM_MPCTL0);
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clks[spll] = imx_clk_pllv1("spll", "prem", regs + CCM_SPCTL0);
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clks[mcu] = imx_clk_divider("mcu", "clk32_premult", regs + CCM_CSCR, 15, 1);
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clks[fclk] = imx_clk_divider("fclk", "mpll", regs + CCM_CSCR, 15, 1);
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clks[hclk] = imx_clk_divider("hclk", "spll", regs + CCM_CSCR, 10, 4);
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clks[clk48m] = imx_clk_divider("clk48m", "spll", regs + CCM_CSCR, 26, 3);
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clks[per1] = imx_clk_divider("per1", "spll", regs + CCM_PCDR, 0, 4);
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clks[per2] = imx_clk_divider("per2", "spll", regs + CCM_PCDR, 4, 4);
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clks[per3] = imx_clk_divider("per3", "spll", regs + CCM_PCDR, 16, 7);
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clks[clko] = imx_clk_mux("clko", regs + CCM_CSCR, 29, 3, clko_sel_clks,
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ARRAY_SIZE(clko_sel_clks));
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clkdev_add_physbase(clks[per1], MX1_TIM1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX1_TIM2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per2], MX1_LCDC_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX1_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per1], MX1_UART2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per2], MX1_CSPI1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[per2], MX1_CSPI2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[hclk], MX1_I2C_BASE_ADDR, NULL);
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return 0;
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}
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static int imx1_ccm_probe(struct device_d *dev)
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{
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void __iomem *regs;
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regs = dev_request_mem_region(dev, 0);
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mx1_clocks_init(regs, 32000);
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return 0;
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}
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static __maybe_unused struct of_device_id imx1_ccm_dt_ids[] = {
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{
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.compatible = "fsl,imx1-ccm",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx1_ccm_driver = {
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.probe = imx1_ccm_probe,
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.name = "imx1-ccm",
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.of_compatible = DRV_OF_COMPAT(imx1_ccm_dt_ids),
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};
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static int imx1_ccm_init(void)
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{
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return platform_driver_register(&imx1_ccm_driver);
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}
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core_initcall(imx1_ccm_init);
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