Not needed as we will handle the additional gate bits as gate. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
327 lines
7.2 KiB
C
327 lines
7.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <driver.h>
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#include <linux/clk.h>
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#include <io.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <clock.h>
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#include <asm-generic/div64.h>
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#include "clk.h"
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#define PLL_NUM_OFFSET 0x10
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#define PLL_DENOM_OFFSET 0x20
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_ENABLE (0x1 << 13)
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#define BM_PLL_BYPASS (0x1 << 16)
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#define BM_PLL_LOCK (0x1 << 31)
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struct clk_pllv3 {
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struct clk clk;
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void __iomem *base;
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bool powerup_set;
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u32 div_mask;
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const char *parent;
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};
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#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
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static int clk_pllv3_enable(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 val;
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int timeout = 10000;
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val = readl(pll->base);
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val &= ~BM_PLL_BYPASS;
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if (pll->powerup_set)
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val |= BM_PLL_POWER;
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else
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val &= ~BM_PLL_POWER;
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writel(val, pll->base);
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/* Wait for PLL to lock */
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while (timeout--) {
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if (readl(pll->base) & BM_PLL_LOCK)
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break;
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}
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if (!timeout)
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return -ETIMEDOUT;
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val = readl(pll->base);
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val |= BM_PLL_ENABLE;
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writel(val, pll->base);
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return 0;
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}
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static void clk_pllv3_disable(struct clk *clk)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 val;
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val = readl(pll->base);
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val &= ~BM_PLL_ENABLE;
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writel(val, pll->base);
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val |= BM_PLL_BYPASS;
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if (pll->powerup_set)
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val &= ~BM_PLL_POWER;
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else
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val |= BM_PLL_POWER;
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writel(val, pll->base);
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}
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static unsigned long clk_pllv3_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 div = readl(pll->base) & pll->div_mask;
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return (div == 1) ? parent_rate * 22 : parent_rate * 20;
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}
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static long clk_pllv3_round_rate(struct clk *clk, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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return (rate >= parent_rate * 22) ? parent_rate * 22 :
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parent_rate * 20;
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}
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static int clk_pllv3_set_rate(struct clk *clk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 val, div;
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if (rate == parent_rate * 22)
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div = 1;
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else if (rate == parent_rate * 20)
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div = 0;
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else
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return -EINVAL;
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val = readl(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel(val, pll->base);
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return 0;
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}
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static const struct clk_ops clk_pllv3_ops = {
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_recalc_rate,
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.round_rate = clk_pllv3_round_rate,
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.set_rate = clk_pllv3_set_rate,
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};
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static unsigned long clk_pllv3_sys_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 div = readl(pll->base) & pll->div_mask;
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return parent_rate * div / 2;
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}
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static long clk_pllv3_sys_round_rate(struct clk *clk, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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unsigned long min_rate = parent_rate * 54 / 2;
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unsigned long max_rate = parent_rate * 108 / 2;
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u32 div;
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if (rate > max_rate)
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rate = max_rate;
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else if (rate < min_rate)
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rate = min_rate;
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div = rate * 2 / parent_rate;
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return parent_rate * div / 2;
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}
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static int clk_pllv3_sys_set_rate(struct clk *clk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long min_rate = parent_rate * 54 / 2;
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unsigned long max_rate = parent_rate * 108 / 2;
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u32 val, div;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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div = rate * 2 / parent_rate;
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val = readl(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel(val, pll->base);
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return 0;
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}
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static const struct clk_ops clk_pllv3_sys_ops = {
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_sys_recalc_rate,
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.round_rate = clk_pllv3_sys_round_rate,
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.set_rate = clk_pllv3_sys_set_rate,
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};
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static unsigned long clk_pllv3_av_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 mfn = readl(pll->base + PLL_NUM_OFFSET);
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u32 mfd = readl(pll->base + PLL_DENOM_OFFSET);
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u32 div = readl(pll->base) & pll->div_mask;
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return (parent_rate * div) + ((parent_rate / mfd) * mfn);
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}
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static long clk_pllv3_av_round_rate(struct clk *clk, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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unsigned long min_rate = parent_rate * 27;
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unsigned long max_rate = parent_rate * 54;
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u32 div;
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u32 mfn, mfd = 1000000;
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u64 temp64;
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if (rate > max_rate)
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rate = max_rate;
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else if (rate < min_rate)
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rate = min_rate;
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div = rate / parent_rate;
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temp64 = (u64) (rate - div * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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return parent_rate * div + parent_rate / mfd * mfn;
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}
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static int clk_pllv3_av_set_rate(struct clk *clk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long min_rate = parent_rate * 27;
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unsigned long max_rate = parent_rate * 54;
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u32 val, div;
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u32 mfn, mfd = 1000000;
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u64 temp64;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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div = rate / parent_rate;
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temp64 = (u64) (rate - div * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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val = readl(pll->base);
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val &= ~pll->div_mask;
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val |= div;
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writel(val, pll->base);
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writel(mfn, pll->base + PLL_NUM_OFFSET);
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writel(mfd, pll->base + PLL_DENOM_OFFSET);
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return 0;
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}
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static const struct clk_ops clk_pllv3_av_ops = {
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_av_recalc_rate,
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.round_rate = clk_pllv3_av_round_rate,
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.set_rate = clk_pllv3_av_set_rate,
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};
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static unsigned long clk_pllv3_enet_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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return 500000000;
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}
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static const struct clk_ops clk_pllv3_enet_ops = {
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_enet_recalc_rate,
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};
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static const struct clk_ops clk_pllv3_mlb_ops = {
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent, void __iomem *base,
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u32 div_mask)
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{
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struct clk_pllv3 *pll;
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const struct clk_ops *ops;
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int ret;
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pll = xzalloc(sizeof(*pll));
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switch (type) {
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case IMX_PLLV3_SYS:
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ops = &clk_pllv3_sys_ops;
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break;
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case IMX_PLLV3_USB:
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ops = &clk_pllv3_ops;
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pll->powerup_set = true;
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break;
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case IMX_PLLV3_AV:
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ops = &clk_pllv3_av_ops;
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break;
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case IMX_PLLV3_ENET:
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ops = &clk_pllv3_enet_ops;
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break;
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case IMX_PLLV3_MLB:
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ops = &clk_pllv3_mlb_ops;
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break;
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default:
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ops = &clk_pllv3_ops;
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}
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pll->base = base;
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pll->div_mask = div_mask;
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pll->parent = parent;
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pll->clk.ops = ops;
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pll->clk.name = name;
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pll->clk.parent_names = &pll->parent;
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pll->clk.num_parents = 1;
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ret = clk_register(&pll->clk);
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if (ret) {
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free(pll);
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return ERR_PTR(ret);
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}
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return &pll->clk;
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}
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