PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it. This patch is backported from http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/commit/cpu/arm_cortexa8/mx6/generic.c?h=imx_v2009.08_3.0.35_4.1.0&id=b7c5badf94ffbe6cd0845efbb75e16e05e3af404 And resolve issues with booting from MMC/SD cards Signed-off-by: Jesús Guitarte <jguitarte@data-modul.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
158 lines
4.8 KiB
C
158 lines
4.8 KiB
C
/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <init.h>
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#include <common.h>
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#include <io.h>
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#include <sizes.h>
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#include <mach/imx6.h>
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#include <mach/generic.h>
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#include <mach/revision.h>
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#include <mach/imx6-anadig.h>
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#include <mach/imx6-regs.h>
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#include <mach/generic.h>
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#define SI_REV 0x260
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void imx6_init_lowlevel(void)
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{
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void __iomem *aips1 = (void *)MX6_AIPS1_ON_BASE_ADDR;
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void __iomem *aips2 = (void *)MX6_AIPS2_ON_BASE_ADDR;
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int is_imx6q = __imx6_cpu_type() == IMX6_CPUTYPE_IMX6Q;
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, aips1);
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writel(0x77777777, aips1 + 0x4);
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writel(0, aips1 + 0x40);
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writel(0, aips1 + 0x44);
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writel(0, aips1 + 0x48);
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writel(0, aips1 + 0x4c);
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writel(0, aips1 + 0x50);
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writel(0x77777777, aips2);
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writel(0x77777777, aips2 + 0x4);
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writel(0, aips2 + 0x40);
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writel(0, aips2 + 0x44);
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writel(0, aips2 + 0x48);
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writel(0, aips2 + 0x4c);
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writel(0, aips2 + 0x50);
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/* enable all clocks */
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writel(0xffffffff, 0x020c4068);
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writel(0xffffffff, 0x020c406c);
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writel(0xffffffff, 0x020c4070);
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writel(0xffffffff, 0x020c4074);
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writel(0xffffffff, 0x020c4078);
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writel(0xffffffff, 0x020c407c);
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writel(0xffffffff, 0x020c4080);
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/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
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* to make sure PFD is working right, otherwise, PFDs may
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* not output clock after reset, MX6DL and MX6SL have added 396M pfd
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* workaround in ROM code, as bus clock need it
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*/
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writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
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BM_ANADIG_PFD_480_PFD2_CLKGATE |
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BM_ANADIG_PFD_480_PFD1_CLKGATE |
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BM_ANADIG_PFD_480_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_SET);
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writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
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(is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
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BM_ANADIG_PFD_528_PFD1_CLKGATE |
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BM_ANADIG_PFD_528_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_SET);
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writel(BM_ANADIG_PFD_480_PFD3_CLKGATE |
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BM_ANADIG_PFD_480_PFD2_CLKGATE |
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BM_ANADIG_PFD_480_PFD1_CLKGATE |
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BM_ANADIG_PFD_480_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_480_CLR);
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writel(BM_ANADIG_PFD_528_PFD3_CLKGATE |
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(is_imx6q ? BM_ANADIG_PFD_528_PFD2_CLKGATE : 0) |
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BM_ANADIG_PFD_528_PFD2_CLKGATE |
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BM_ANADIG_PFD_528_PFD1_CLKGATE |
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BM_ANADIG_PFD_528_PFD0_CLKGATE,
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MX6_ANATOP_BASE_ADDR + HW_ANADIG_PFD_528_CLR);
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}
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int imx6_init(void)
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{
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const char *cputypestr;
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u32 rev;
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u32 mx6_silicon_revision;
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imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
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rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
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switch (rev & 0xff) {
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case 0x00:
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mx6_silicon_revision = IMX_CHIP_REV_1_0;
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break;
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case 0x01:
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mx6_silicon_revision = IMX_CHIP_REV_1_1;
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break;
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case 0x02:
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mx6_silicon_revision = IMX_CHIP_REV_1_2;
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break;
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default:
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mx6_silicon_revision = IMX_CHIP_REV_UNKNOWN;
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}
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switch (imx6_cpu_type()) {
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case IMX6_CPUTYPE_IMX6Q:
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cputypestr = "i.MX6 Quad";
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break;
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case IMX6_CPUTYPE_IMX6D:
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cputypestr = "i.MX6 Dual";
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break;
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case IMX6_CPUTYPE_IMX6DL:
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cputypestr = "i.MX6 DualLite";
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break;
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case IMX6_CPUTYPE_IMX6S:
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cputypestr = "i.MX6 Solo";
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break;
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default:
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cputypestr = "unknown i.MX6";
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break;
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}
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imx_set_silicon_revision(cputypestr, mx6_silicon_revision);
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return 0;
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}
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int imx6_devices_init(void)
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{
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add_generic_device("imx-iomuxv3", 0, NULL, MX6_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpt", 0, NULL, MX6_GPT_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 1, NULL, MX6_GPIO2_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 2, NULL, MX6_GPIO3_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 3, NULL, MX6_GPIO4_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx31-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx21-wdt", 0, NULL, MX6_WDOG1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("imx6-usb-misc", 0, NULL, MX6_USBOH3_USB_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL);
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return 0;
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}
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