187 lines
4.9 KiB
C
187 lines
4.9 KiB
C
/**
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* @file
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* @brief Provide Generic GPMC configuration option
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*
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* This file contains the generic GPMC implementation
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*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <clock.h>
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#include <init.h>
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#include <io.h>
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#include <errno.h>
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#include <mach/omap3-silicon.h>
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#include <mach/omap4-silicon.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/gpmc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/generic.h>
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/**
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* @brief Do a Generic initialization of GPMC. if you choose otherwise,
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* Use gpmc registers to modify the values. The defaults configured are:
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* No idle, L3 free running, no timeout and no IRQs.
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* we allow for gpmc_config data to be programmed, and will also disable
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* ALL CS configurations
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*
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* @param cfg - GPMC_CFG register value
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*
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* @return void
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*/
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void gpmc_generic_init(unsigned int cfg)
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{
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uint64_t start;
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void __iomem *reg = GPMC_REG(CONFIG7_0);
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char x = 0;
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debug("gpmccfg=0x%x\n", cfg);
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/* Generic Configurations */
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/* reset gpmc */
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start = get_time_ns();
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/* No idle, L3 clock free running */
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writel(0x12, GPMC_REG(SYS_CONFIG));
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while (!readl(GPMC_REG(SYS_STATUS)))
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if (is_timeout(start, MSECOND)) {
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printf("timeout on gpmc reset\n");
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break;
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}
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/* No Timeout */
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writel(0x00, GPMC_REG(TIMEOUT_CONTROL));
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/* No IRQs */
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writel(0x00, GPMC_REG(IRQ_ENABLE));
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/* Write the gpmc_config value */
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writel(cfg, GPMC_REG(CFG));
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/* Disable all CS - prevents remaps
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* But NEVER run me in XIP mode! I will Die!
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*/
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while (x < GPMC_NUM_CS) {
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debug("gpmccs=%d Reg:0x%p <-0x0\n", x, reg);
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writel(0x0, reg);
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reg += GPMC_CONFIG_CS_SIZE;
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x++;
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}
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/* Give me a while to settle things down */
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mdelay(1);
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}
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EXPORT_SYMBOL(gpmc_generic_init);
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/**
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* @brief Configure the registers and enable a single CS.
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*
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* @param cs chip select index
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* @param config gpmc_config structure describing the CS params
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*
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* @return void
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*/
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void gpmc_cs_config(char cs, struct gpmc_config *config)
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{
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void __iomem *reg = GPMC_REG(CONFIG1_0) + (cs * GPMC_CONFIG_CS_SIZE);
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unsigned char x = 0;
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uint32_t config7;
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debug("%s: cs=%d base=0x%08x size=0x%08x\n", __func__,
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cs, config->base, config->size);
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/* Disable the CS before reconfiguring */
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writel(0x0, GPMC_REG(CONFIG7_0) + (cs * GPMC_CONFIG_CS_SIZE));
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mdelay(1); /* Settling time */
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/* Write the CFG1-6 regs */
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while (x < 6) {
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debug("gpmccfg%d Reg:0x%p <-0x%08x, old 0x%08x\n",
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x, reg, config->cfg[x], readl(reg));
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writel(config->cfg[x], reg);
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reg += GPMC_CONFIG_REG_OFF;
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x++;
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}
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config7 = (0x1 << 6) | /* CS enable */
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((config->size & 0xF) << 8) | /* Size */
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((config->base >> 24) & 0x3F);
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debug("gpmccfg%d Reg:0x%p <-0x%08x, old 0x%08x\n",
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x, reg, config7, readl(reg));
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writel(config7, reg);
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mdelay(1); /* Settling time */
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}
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EXPORT_SYMBOL(gpmc_cs_config);
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#define CS_NUM_SHIFT 24
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#define ENABLE_PREFETCH (0x1 << 7)
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#define DMA_MPU_MODE 2
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/**
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* gpmc_prefetch_enable - configures and starts prefetch transfer
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* @cs: cs (chip select) number
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* @fifo_th: fifo threshold to be used for read/ write
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* @dma_mode: dma mode enable (1) or disable (0)
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* @u32_count: number of bytes to be transferred
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* @is_write: prefetch read(0) or write post(1) mode
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*/
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int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
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unsigned int u32_count, int is_write)
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{
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if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
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pr_err("gpmc: fifo threshold is not supported\n");
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return -EINVAL;
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}
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/* Set the amount of bytes to be prefetched */
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writel(u32_count, GPMC_REG(PREFETCH_CONFIG2));
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/* Set dma/mpu mode, the prefetch read / post write and
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* enable the engine. Set which cs is has requested for.
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*/
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writel(((cs << CS_NUM_SHIFT) | PREFETCH_FIFOTHRESHOLD(fifo_th) |
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ENABLE_PREFETCH | (dma_mode << DMA_MPU_MODE) |
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(0x1 & is_write)),
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GPMC_REG(PREFETCH_CONFIG1));
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/* Start the prefetch engine */
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writel(0x1, GPMC_REG(PREFETCH_CONTROL));
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return 0;
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}
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EXPORT_SYMBOL(gpmc_prefetch_enable);
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/**
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* gpmc_prefetch_reset - disables and stops the prefetch engine
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*/
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int gpmc_prefetch_reset(int cs)
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{
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u32 config1;
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/* check if the same module/cs is trying to reset */
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config1 = readl(GPMC_REG(PREFETCH_CONFIG1));
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if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
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return -EINVAL;
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/* Stop the PFPW engine */
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writel(0x0, GPMC_REG(PREFETCH_CONTROL));
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/* Reset/disable the PFPW engine */
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writel(0x0, GPMC_REG(PREFETCH_CONFIG1));
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return 0;
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}
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EXPORT_SYMBOL(gpmc_prefetch_reset);
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