And use it inside struct fb_info. This struct has the advantage that the supported modes can be passed around in a single pointer. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
418 lines
11 KiB
C
418 lines
11 KiB
C
/*
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* Copyright (C) 2010 Juergen Beisert
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* Copyright (C) 2011 Alexey Galakhov
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*
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* This driver is based on a patch found in the web:
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* (C) Copyright 2006 by OpenMoko, Inc.
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* Author: Harald Welte <laforge at openmoko.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <fb.h>
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#include <driver.h>
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#include <malloc.h>
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#include <errno.h>
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#include <io.h>
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#include <mach/s3c-generic.h>
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#include <mach/s3c24xx-fb.h>
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#define LCDCON1 0x00
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# define PNRMODE(x) (((x) & 3) << 5)
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# define BPPMODE(x) (((x) & 0xf) << 1)
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# define SET_CLKVAL(x) (((x) & 0x3ff) << 8)
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# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff)
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# define ENVID (1 << 0)
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#define LCDCON2 0x04
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# define SET_VBPD(x) (((x) & 0xff) << 24)
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# define SET_LINEVAL(x) (((x) & 0x3ff) << 14)
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# define SET_VFPD(x) (((x) & 0xff) << 6)
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# define SET_VSPW(x) ((x) & 0x3f)
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#define LCDCON3 0x08
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# define SET_HBPD(x) (((x) & 0x7f) << 19)
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# define SET_HOZVAL(x) (((x) & 0x7ff) << 8)
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# define SET_HFPD(x) ((x) & 0xff)
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#define LCDCON4 0x0c
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# define SET_HSPW(x) ((x) & 0xff)
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#define LCDCON5 0x10
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# define BPP24BL (1 << 12)
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# define FRM565 (1 << 11)
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# define INV_CLK (1 << 10)
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# define INV_HS (1 << 9)
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# define INV_VS (1 << 8)
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# define INV_DTA (1 << 7)
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# define INV_DE (1 << 6)
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# define INV_PWREN (1 << 5)
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# define INV_LEND (1 << 4)
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# define ENA_PWREN (1 << 3)
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# define ENA_LEND (1 << 2)
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# define BSWP (1 << 1)
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# define HWSWP (1 << 0)
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#define LCDSADDR1 0x14
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# define SET_LCDBANK(x) (((x) & 0x1ff) << 21)
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# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff)
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# define SET_LCDBASEU(x) ((x) & 0x1fffff)
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# define GET_LCDBASEU(x) ((x) & 0x1fffff)
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#define LCDSADDR2 0x18
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# define SET_LCDBASEL(x) ((x) & 0x1fffff)
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# define GET_LCDBASEL(x) ((x) & 0x1fffff)
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#define LCDSADDR3 0x1c
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# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11)
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# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff)
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# define SET_PAGE_WIDTH(x) ((x) & 0x3ff)
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# define GET_PAGE_WIDTH(x) ((x) & 0x3ff)
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#define RED_LUT 0x20
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#define GREEN_LUT 0x24
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#define BLUE_LUT 0x28
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#define DITHMODE 0x4c
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#define TPAL 0x50
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#define LCDINTPND 0x54
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#define LCDSRCPND 0x58
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#define LCDINTMSK 0x5c
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# define FIWSEL (1 << 2)
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# define INT_FrSyn (1 << 1)
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# define INT_FiCnt (1 << 0)
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#define TCONSEL 0x60
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#define RED 0
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#define GREEN 1
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#define BLUE 2
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#define TRANSP 3
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struct s3cfb_info {
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void __iomem *base;
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unsigned memory_size;
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struct fb_info info;
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struct device_d *hw_dev;
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int passive_display;
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void (*enable)(int enable);
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};
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/* the RGB565 true colour mode */
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static const struct fb_bitfield def_rgb565[] = {
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[RED] = {
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.offset = 11,
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.length = 5,
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},
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[GREEN] = {
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.offset = 5,
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.length = 6,
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},
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[BLUE] = {
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.offset = 0,
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.length = 5,
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},
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[TRANSP] = { /* no support for transparency */
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.length = 0,
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}
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};
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/* the RGB888 true colour mode */
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static const struct fb_bitfield def_rgb888[] = {
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[RED] = {
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.offset = 16,
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.length = 8,
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},
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[GREEN] = {
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.offset = 8,
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.length = 8,
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},
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[BLUE] = {
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.offset = 0,
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.length = 8,
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},
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[TRANSP] = { /* no support for transparency */
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.length = 0,
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}
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};
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/**
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* @param fb_info Framebuffer information
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*/
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static void s3cfb_enable_controller(struct fb_info *fb_info)
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{
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struct s3cfb_info *fbi = fb_info->priv;
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uint32_t con1;
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con1 = readl(fbi->base + LCDCON1);
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con1 |= ENVID;
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writel(con1, fbi->base + LCDCON1);
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if (fbi->enable)
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fbi->enable(1);
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}
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/**
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* @param fb_info Framebuffer information
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*/
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static void s3cfb_disable_controller(struct fb_info *fb_info)
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{
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struct s3cfb_info *fbi = fb_info->priv;
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uint32_t con1;
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if (fbi->enable)
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fbi->enable(0);
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con1 = readl(fbi->base + LCDCON1);
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con1 &= ~ENVID;
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writel(con1, fbi->base + LCDCON1);
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}
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/**
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* Prepare the video hardware for a specified video mode
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* @param fb_info Framebuffer information
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* @return 0 on success
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*/
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static int s3cfb_activate_var(struct fb_info *fb_info)
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{
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struct s3cfb_info *fbi = fb_info->priv;
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struct fb_videomode *mode = fb_info->mode;
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unsigned size, hclk, div;
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uint32_t con1, con2, con3, con4, con5 = 0;
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if (fbi->passive_display != 0) {
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dev_err(fbi->hw_dev, "Passive displays are currently not supported\n");
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return -EINVAL;
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}
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/*
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* we need at least this amount of memory for the framebuffer
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*/
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size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3);
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if (fbi->memory_size != size || fb_info->screen_base == NULL) {
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if (fb_info->screen_base)
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free(fb_info->screen_base);
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fbi->memory_size = 0;
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fb_info->screen_base = malloc(size);
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if (! fb_info->screen_base)
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return -ENOMEM;
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memset(fb_info->screen_base, 0, size);
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fbi->memory_size = size;
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}
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/* ensure video output is _off_ */
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writel(0x00000000, fbi->base + LCDCON1);
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hclk = s3c_get_hclk() / 1000U; /* hclk in kHz */
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div = hclk / PICOS2KHZ(mode->pixclock);
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if (div < 3)
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div = 3;
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/* pixel clock is: (hclk) / ((div + 1) * 2) */
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div += 1;
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div >>= 1;
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div -= 1;
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con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */
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switch (fb_info->bits_per_pixel) {
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case 16:
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con1 |= BPPMODE(12);
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con5 |= FRM565;
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con5 |= HWSWP;
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fb_info->red = def_rgb565[RED];
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fb_info->green = def_rgb565[GREEN];
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fb_info->blue = def_rgb565[BLUE];
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fb_info->transp = def_rgb565[TRANSP];
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break;
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case 24:
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con1 |= BPPMODE(13);
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/* con5 |= BPP24BL; */ /* FIXME maybe needed, check alignment */
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fb_info->red = def_rgb888[RED];
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fb_info->green = def_rgb888[GREEN];
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fb_info->blue = def_rgb888[BLUE];
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fb_info->transp = def_rgb888[TRANSP];
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break;
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default:
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dev_err(fbi->hw_dev, "Invalid bits per pixel value: %u\n", fb_info->bits_per_pixel);
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return -EINVAL;
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}
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/* 'normal' in register description means positive logic */
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if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
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con5 |= INV_HS;
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if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
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con5 |= INV_VS;
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if (!(mode->sync & FB_SYNC_DE_HIGH_ACT))
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con5 |= INV_DE;
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if (mode->sync & FB_SYNC_CLK_INVERT)
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con5 |= INV_CLK; /* display should latch at the rising edge */
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if (mode->sync & FB_SYNC_DATA_INVERT)
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con5 |= INV_DTA;
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if (mode->sync & FB_SYNC_INVERT_PWREN)
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con5 |= INV_PWREN;
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if (mode->sync & FB_SYNC_INVERT_LEND)
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con5 |= INV_LEND;
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if (mode->sync & FB_SYNC_USE_PWREN)
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con5 |= ENA_PWREN; /* FIXME should this be done conditionally/later? */
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if (mode->sync & FB_SYNC_USE_LEND)
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con5 |= ENA_LEND;
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if (mode->sync & FB_SYNC_SWAP_BYTES)
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con5 ^= BSWP;
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if (mode->sync & FB_SYNC_SWAP_HW)
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con5 ^= HWSWP;
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/* vertical timing */
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con2 = SET_VBPD(mode->upper_margin - 1) |
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SET_LINEVAL(mode->yres - 1) |
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SET_VFPD(mode->lower_margin - 1) |
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SET_VSPW(mode->vsync_len - 1);
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/* horizontal timing */
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con3 = SET_HBPD(mode->left_margin - 1) |
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SET_HOZVAL(mode->xres - 1) |
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SET_HFPD(mode->right_margin - 1);
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con4 = SET_HSPW(mode->hsync_len - 1);
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/* basic timing setup */
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writel(con1, fbi->base + LCDCON1);
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dev_dbg(fbi->hw_dev, "writing %08X into %p (con1)\n", con1, fbi->base + LCDCON1);
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writel(con2, fbi->base + LCDCON2);
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dev_dbg(fbi->hw_dev, "writing %08X into %p (con2)\n", con2, fbi->base + LCDCON2);
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writel(con3, fbi->base + LCDCON3);
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dev_dbg(fbi->hw_dev, "writing %08X into %p (con3)\n", con3, fbi->base + LCDCON3);
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writel(con4, fbi->base + LCDCON4);
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dev_dbg(fbi->hw_dev, "writing %08X into %p (con4)\n", con4, fbi->base + LCDCON4);
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writel(con5, fbi->base + LCDCON5);
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dev_dbg(fbi->hw_dev, "writing %08X into %p (con5)\n", con5, fbi->base + LCDCON5);
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dev_dbg(fbi->hw_dev, "setting up the fb baseadress to %p\n", fb_info->screen_base);
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/* framebuffer memory setup */
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writel((unsigned)fb_info->screen_base >> 1, fbi->base + LCDSADDR1);
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size = mode->xres * (fb_info->bits_per_pixel >> 3) * (mode->yres);
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writel(SET_LCDBASEL(((unsigned)fb_info->screen_base + size) >> 1), fbi->base + LCDSADDR2);
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writel(SET_OFFSIZE(0) |
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SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4),
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fbi->base + LCDSADDR3);
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writel(FIWSEL | INT_FrSyn | INT_FiCnt, fbi->base + LCDINTMSK);
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return 0;
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}
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/**
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* Print some information about the current hardware state
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* @param hw_dev S3C video device
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*/
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static void s3cfb_info(struct device_d *hw_dev)
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{
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uint32_t con1, addr1, addr2, addr3;
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struct s3cfb_info *fbi = hw_dev->priv;
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con1 = readl(fbi->base + LCDCON1);
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addr1 = readl(fbi->base + LCDSADDR1);
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addr2 = readl(fbi->base + LCDSADDR2);
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addr3 = readl(fbi->base + LCDSADDR3);
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printf(" Video hardware info:\n");
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printf(" Video clock is running at %u Hz\n", s3c_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
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printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
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printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
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printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
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printf(" Virtual screen offset size: %u half words\n", GET_OFFSIZE(addr3));
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printf(" Virtual screen page width: %u half words\n", GET_PAGE_WIDTH(addr3));
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}
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/*
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* There is only one video hardware instance available.
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* It makes no sense to dynamically allocate this data
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*/
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static struct fb_ops s3cfb_ops = {
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.fb_activate_var = s3cfb_activate_var,
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.fb_enable = s3cfb_enable_controller,
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.fb_disable = s3cfb_disable_controller,
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};
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static struct s3cfb_info fbi = {
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.info = {
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.fbops = &s3cfb_ops,
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},
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};
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static int s3cfb_probe(struct device_d *hw_dev)
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{
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struct s3c_fb_platform_data *pdata = hw_dev->platform_data;
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int ret;
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if (! pdata)
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return -ENODEV;
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fbi.base = dev_request_mem_region(hw_dev, 0);
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writel(0, fbi.base + LCDCON1);
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writel(0, fbi.base + LCDCON5); /* FIXME not 0 for some displays */
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/* just init */
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fbi.info.priv = &fbi;
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/* add runtime hardware info */
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fbi.hw_dev = hw_dev;
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hw_dev->priv = &fbi;
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/* add runtime video info */
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fbi.info.modes.modes = pdata->mode_list;
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fbi.info.modes.num_modes = pdata->mode_cnt;
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fbi.info.mode = &fbi.info.modes.modes[0];
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fbi.info.xres = fbi.info.mode->xres;
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fbi.info.yres = fbi.info.mode->yres;
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if (pdata->bits_per_pixel)
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fbi.info.bits_per_pixel = pdata->bits_per_pixel;
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else
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fbi.info.bits_per_pixel = 16;
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fbi.passive_display = pdata->passive_display;
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fbi.enable = pdata->enable;
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if (IS_ENABLED(CONFIG_DRIVER_VIDEO_S3C_VERBOSE))
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hw_dev->info = s3cfb_info;
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ret = register_framebuffer(&fbi.info);
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if (ret != 0) {
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dev_err(hw_dev, "Failed to register framebuffer\n");
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return -EINVAL;
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}
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return 0;
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}
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static struct driver_d s3cfb_driver = {
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.name = "s3c_fb",
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.probe = s3cfb_probe,
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};
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device_platform_driver(s3cfb_driver);
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/**
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* The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) LC displays
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*
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* The driver itself currently supports only active TFT LC displays in the follwing manner:
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*
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* * True colours
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* - 16 bpp
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* - 24 bpp (untested)
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*/
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