f2e2e596a2
This adds barebox common clk support loosely based on the Kernel common clk support. differences are: - barebox does not need prepare/unprepare - no parent rate propagation for set_rate - struct clk is not really encapsulated from the drivers Along with the clk support we have support for some basic clk building blocks: - clk-fixed - clk-fixed-factor - clk-mux - clk-divider clk-fixed and clk-fixed-factor are completely generic, clk-mux and clk-divider are currently the way i.MX muxes/dividers are implemented. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
/*
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* clk-divider.c - generic barebox clock support. Based on Linux clk support
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*
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* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <malloc.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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struct clk_divider {
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struct clk clk;
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u8 shift;
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u8 width;
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void __iomem *reg;
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const char *parent;
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};
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static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *div = container_of(clk, struct clk_divider, clk);
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unsigned int val, divval;
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if (rate > parent_rate)
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rate = parent_rate;
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if (!rate)
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rate = 1;
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divval = DIV_ROUND_UP(parent_rate, rate);
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if (divval > (1 << div->width))
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divval = 1 << (div->width);
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divval--;
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val = readl(div->reg);
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val &= ~(((1 << div->width) - 1) << div->shift);
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val |= divval << div->shift;
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writel(val, div->reg);
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return 0;
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}
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static unsigned long clk_divider_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_divider *div = container_of(clk, struct clk_divider, clk);
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unsigned int val;
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val = readl(div->reg) >> div->shift;
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val &= (1 << div->width) - 1;
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val++;
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return parent_rate / val;
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}
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struct clk_ops clk_divider_ops = {
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.set_rate = clk_divider_set_rate,
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.recalc_rate = clk_divider_recalc_rate,
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};
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struct clk *clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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struct clk_divider *div = xzalloc(sizeof(*div));
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int ret;
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div->shift = shift;
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div->reg = reg;
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div->width = width;
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div->parent = parent;
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div->clk.ops = &clk_divider_ops;
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div->clk.name = name;
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div->clk.parent_names = &div->parent;
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div->clk.num_parents = 1;
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ret = clk_register(&div->clk);
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if (ret) {
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free(div);
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return ERR_PTR(ret);
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}
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return &div->clk;
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}
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